Abstract
The goal of this work is to overcome the major impediments of tunnel FET such as the inherent ambipolar current (I AMB) and the lower ON current (I ON). To suppress the I AMB, gate drain overlap (GDO) engineering scheme has been incorporated over the cylindrical gate all around TFET (GAA-TFET). However, to enhance the I ON, heterogate dielectrics (HD) are used in the gate oxide region. Results indicate that an appreciably reduced I AMB and significantly enhanced I ON has been obtained with the amalgamation of GDO and HD, respectively, onto GAA-TFET. Further, the effect of GDO length (L ov) has also been studied. Quantitative analysis of ambipolarity factor “α” reveals that at large L ov, “α” improves. It is found that GDO degrades the high-frequency (HF) performance such as cutoff frequency (f T) of the device, because of the enhanced parasitic capacitances. To surpass the deterioration at HF caused by GDO, the dielectric over GDO region has been altered, and it has been analyzed that by inserting a material of low-dielectric constant (k = 1) and parasitic capacitances of the device reduces, resulting into enhancement in f T. Moreover, the low-k dielectric inserted over L ov reduces the I AMB supplementary, along with enhanced f T. Suppressed I AMB and enhanced f T of GDO–HD–GAA-TFET with low-k dielectric over L ov make it adequate for application in HF and digital circuitry.
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References
J. Goldberger, A.I. Hochbaum, R. Fan, P. Yang, Silicon vertically integrated nanowire field effect transistors. Nano Lett. 6, 973–977 (2006)
J. Madan, R. Chaujar, Interfacial Charge Analysis of Heterogeneous Gate Dielectric-Gate All Around-Tunnel FET for Improved Device Reliability. IEEE Trans. Device Mater. Reliab. 16, 227–234 (2016)
K. Mao, T. Mizutani, A. Kumar, T. Saraya, T. Hiramoto, Suppression of within-device variability in intrinsic channel tri-gate silicon nanowire metal–oxide–semiconductor field-effect transistors. Jpn. J. Appl. Phys. 51, 02BC06 (2012)
N. Singh, A. Agarwal, L. Bera, T. Liow, R. Yang, S. Rustagi, C. Tung, R. Kumar, G. Lo, N. Balasubramanian, High-performance fully depleted silicon nanowire (diameter ≤ 5 nm) gate-all-around CMOS devices. IEEE Electron Device Lett. 27, 383–386 (2006)
W.Y. Choi, W. Lee, Hetero-gate-dielectric tunneling field-effect transistors. IEEE Trans. Electron Devices 57, 2317–2319 (2010)
A.S. Verhulst, W.G. Vandenberghe, K. Maex, G. Groeseneken, Tunnel field-effect transistor without gate-drain overlap. Appl. Phys. Lett. 91, 053102 (2007)
K. Boucart, A.M. Ionescu, Double-gate tunnel FET with high-gate dielectric, (2007)
S. Cho, M.-C. Sun, G. Kim, T.I. Kamins, B.-G. Park, J.S. Harris Jr., Design optimization of a type-I heterojunction tunneling field-effect transistor (I-HTFET) for high performance logic technology. J. Semiconductor Technology and Science 11, 182–189 (2011)
A. Gao, N. Lu, Y. Wang, T. Li, Robust ultrasensitive tunneling-FET biosensor for point-of-care diagnostics, Scientific reports, 6 (2016)
H.-C. Lin, M.-F. Wang, C.-Y. Lu, T.-Y. Huang, Ambipolar Schottky barrier silicon-on-insulator metal–oxide–semiconductor transistors. Solid-State Electronics 47, 247–251 (2003)
J. Madan, R. Chaujar, Palladium gate all around-Hetero dielectric-tunnel FET based highly sensitive hydrogen gas sensor, Superlattices and Microstructures, (2016)
J. Madan, R. Gupta, R. Chaujar, Performance investigation of heterogeneous gate dielectric-gate metal engineered–gate all around-tunnel FET for RF applications, Microsystem Technologies, (2016) 1–10
A. Mallik, A. Chattopadhyay, S. Guin, A. Karmakar, Impact of a spacer–drain overlap on the characteristics of a silicon tunnel field-effect transistor based on vertical tunneling. IEEE Trans. Electron Devices 60, 935–943 (2013)
A. Naderi, P. Keshavarzi, The effects of source/drain and gate overlap on the performance of carbon nanotube field effect transistors. Superlattices Microstruct. 52, 962–976 (2012)
R. Gandhi, Z. Chen, N. Singh, K. Banerjee, S. Lee, CMOS-Compatible Vertical-Silicon-Nanowire Gate-All-Around p-Type Tunneling FETs With-mV/decade Subthreshold Swing. IEEE Electron Device Lett. 32, 1504–1506 (2011)
P.-F. Wang, K. Hilsenbeck, T. Nirschl, M. Oswald, C. Stepper, M. Weis, D. Schmitt-Landsiedel, W. Hansch, Complementary tunneling transistor for low power application. Solid-State Electronics 48, 2281–2286 (2004)
A.U.S. Manual, Silvaco, Santa Clara, CA, (2010)
A. Biswas, S.S. Dan, C. Le Royer, W. Grabinski, A.M. Ionescu, TCAD simulation of SOI TFETs and calibration of non-local band-to-band tunneling model. Microelectron. Eng. 98, 334–337 (2012)
Z. Chen, H. Yu, N. Singh, N. Shen, R. Sayanthan, G. Lo, D.-L. Kwong, Demonstration of tunneling FETs based on highly scalable vertical silicon nanowires. IEEE Electron Device Lett. 30, 754–756 (2009)
Y.-S. Choi, T.-P. Rhee, K.-D. Yoo, T. Won, A new submicron MOSFET technology with Gate Overlap on Twin Oxide (GOTO) LDD structure. Microelectron. Eng. 15, 253–256 (1991)
J. Madan, R. Gupta, R. Chaujar, Analytical drain current formulation for gate dielectric engineered dual material gate-gate all around-tunneling field effect transistor. Jpn. J. Appl. Phys. 54, 094202 (2015)
J. Madan, R. Gupta, R. Chaujar, Mathematical modeling insight of hetero gate dielectric-dual material gate-GAA-tunnel FET for VLSI/analog applications, Microsystem Technologies, (2016) 1–8
Y. Yang, X. Tong, L.-T. Yang, P.-F. Guo, L. Fan, Y.-C. Yeo, Tunneling field-effect transistor: capacitance components and modeling. IEEE Electron Device Lett. 31, 752–754 (2010)
A. Shaker, M. Ossaimee, A. Zekry, M. Abouelatta, Influence of gate overlap engineering on ambipolar and high frequency characteristics of tunnel-CNTFET. Superlattices Microstruct. 86, 518–530 (2015)
S. Mookerjea, R. Krishnan, S. Datta, V. Narayanan, On enhanced Miller capacitance effect in interband tunnel transistors. IEEE Electron Device Lett. 30, 1102–1104 (2009)
Acknowledgments
Authors would like to thank to Microelectronics Research Lab, Department of Engineering Physics Delhi Technological University, for carrying out this work. One of the authors (Jaya Madan) would like to thank University Grants Commission, Govt. of India, for providing the necessary financial assistance during the course of this research work.
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Madan, J., Chaujar, R. Gate drain-overlapped-asymmetric gate dielectric-GAA-TFET: a solution for suppressed ambipolarity and enhanced ON state behavior. Appl. Phys. A 122, 973 (2016). https://doi.org/10.1007/s00339-016-0510-0
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DOI: https://doi.org/10.1007/s00339-016-0510-0