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Investigation of electrical/analog performance and reliability of gate metal and source pocket engineered DG-TFET

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Abstract

Although Tunnel Field Effect Transistors (TFET) offer low leakage current and allow good scalability, but they suffer from low ON-current. Present research paper focuses on the designing of an industry ready TFET that can operate efficiently at nano-scales allowing the fabrication of a smaller and more energy efficient overall device. To achieve the same, the Gate Metal Engineering (GME) and n+ Source Pocket (SP) schemes have been integrated on Double-Gate TFET (DG-TFET). For a distinct examination of the merits of GME and SP, 4 types of TFET architectures, namely the DG-TFET, GME-DG-TFET, SP-DG-TFET and GME-SP-DG-TFET (which amalgamates the merits of both GME and SP engineering) are investigated. All these device architectures are examined in terms of their electrical characteristics and analog parameters. GME-SP-DG-TFET (being superior among the four) is further analyzed under the presence of interface fixed charges (FC) of different polarity to affirm its reliability. Investigations of this device structure reveal that the positive FC are more noxious for the device as compared to negative FC. However, the enhanced flatband voltage under the negative FC translates to the high gate bias requirement to turn the device ON. Observance of only marginal variations in the parasitic capacitances and efficiency of the GME-SP-DG-TFET device in the presence of FC (both positive/negative) signifies its immunity and promises enhanced reliability. A remarkable improvement of the ION/IOFF by two order of magnitude (from 1010 to 1012) and a decrease in Vth by 27.71% observed for GME-SP-DG-TFET as compared to DG-TFET along with the improved reliability makes the former an efficient candidate for low power analog/RF applications.

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Acknowledgements

Authors would like to thank Microelectronics Research Lab, Department of Applied Physics, Delhi Technological University and all members of VLSI Center of Excellence at Chitkara University for their support in this work.

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Authors and Affiliations

  1. VLSI Centre of Excellence, Chitkara University Institute of Engineering and Technology, Chitkara University, Punjab, India

    Jaya Madan, Rahul Pandey & Rajnish Sharma

  2. Department of Applied Physics, Delhi Technological University, Bawana Road, Delhi, 110042, India

    Rishu Chaujar

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  1. Jaya Madan
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  2. Rahul Pandey
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  4. Rishu Chaujar
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Correspondence to Rahul Pandey or Rajnish Sharma.

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Madan, J., Pandey, R., Sharma, R. et al. Investigation of electrical/analog performance and reliability of gate metal and source pocket engineered DG-TFET. Microsyst Technol 27, 4073–4085 (2021). https://doi.org/10.1007/s00542-020-04845-2

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