An evolutionary-based design methodology for performance enhancement of a folded-cascode OTA using symbiotic organisms search algorithm and g_m/I_D technique

Abstract

In this paper, a new population-based evolutionary technique namely symbiotic organisms search (SOS) optimisation algorithm is proposed to optimize the design variables of transistors used in analog circuit. Here length and width of the transistors are considered to be the design variables, the optimisation of which minimizes the input-referred noise, total MOSFET area, and power consumption. This algorithm is quite useful in solving optimization problems but it suffers from higher computational time. Thus in order to minimize the computational time along with SOS algorithm, g_m/I_D design methodology is used. The proposed method not only guarantees appropriate bias conditions but also estimates the reduced search spaces for the design variables of the MOSFETs. To analyse the performance of SOS algorithm along with g_m/I_D design methodology, a low noise differential folded-cascode operational transconductance amplifier has been designed and verified using Cadence Spectre circuit simulator in UMC 0.18 µm CMOS process and MATLAB. From the optimisation results, it is observed that the g_m/I_D method combined with SOS algorithm converges earlier than SOS alone. The total computational time of simulation obtained using the proposed method is 8.59 s while errors found are less than 8%. Hence, this method not only reduces computational time but also improves the accuracy of the circuit design.

1 Introduction

Due to the rapid advancements in CMOS technologies, the design of analog integrated circuits need a more accurate and faster design methodology to meet certain targeted specifications [1].

In order to achieve targeted specifications most of the IC designers work directly on the design task to determine the width (W) and length (L) of the MOSFETs and other values of circuit elements. However, as pointed out in [2,3,4,5], the variation of sizes W and L not only makes the sizing the task difficult to perform when obtained manually but also takes a lot of time to process when evolutionary algorithms(EAs) are implemented especially in the expanded search space [6].

Multi-objective optimization algorithms shown their usefulness in solving the problems related to optimization in recent times. Some of the recent articles [7, 8] describe that CMOS amplifiers can be better optimized using EAs. But the major drawback with EAs is that the computational time increases with the increase in search space. As an alternative to the analog design optimization method, g_m/I_D methodology is used to find the optimum circuit parameters [9,10,11]. The g_m/I_D methodology has been extensively used for sizing of low power and low noise CMOS transistors. In this method instead of using simple models, a simulated dataset is used to describe the behavior of transistors. Different transistor parameters and figure-of-merits are characterized by the dataset which changes with g_m/I_D. Here, the primary design variable considered is g_m/I_D rather than overdrive voltage which is used in general for a square law based design [12,13,14]. Thus, the combination of the g_m/I_D lookup table approach and the evolutionary based optimization is considered for this work. With the use of g_m/I_D design technique and EAs simultaneously not only the biasing conditions of the transistors are assured but also automatic improvements in sizing of transistors are ascertained [15].

Some of the well accepted optimization algorithms are Particle Swarm Optimization (PSO) [16,17,18,19], Genetic Algorithm (GA) [20] and Ant Colony Optimization (ACO) [21] etc. The main advantage of these optimisation algorithms are its ease of implementation. But the drawbacks of traditional algorithms are sluggishness and premature convergence. To solve these problems, a SOS optimization technique is proposed, which has overcome the disadvantages faced by those algorithms. The performance after using this algorithm is analysed using an optimized folded-cascode OTA. In comparison with other evolutionary algorithms, it provides better particle search efficiency without advanced complexity and faster convergence speed. But for a complicated topology, the SOS based optimization often increases the computational time and thus it becomes difficult to analyse the physical behaviour for different circumstances [22, 23]. The g_m/I_D method shows its effectiveness regarding improvement of the simulation time of SOS algorithm by reduction of search space for obtaining the optimum size of the MOSFETs. Article [24], shows the usefulness of the g_m/I_D methodology with the Adaptive Particle Swarm Optimization (APSO) algorithm to optimize a multistage amplifier.

In this paper, we propose a technique that combines SOS algorithm with the g_m/I_D design methodology for the optimal design of differential folded-cascode OTA circuit. The advantages of this approach are: bias conditions of each transistor are ensured, the computational time for SOS is reduced and it takes less time to evaluate the fitness functions. Here, to find out the dimensions and the biasing conditions of the transistors MATLAB is used. The performance of the circuit is validated using Cadence Spectre tool.

The rest of the paper is organized as follows: introduction of g_m/I_D methodology and formulation of the gate-referred noise of a transistor is discussed in Sect. 2.

Discussions on the SOS algorithm are made in Sect. 3. The systematic design steps of differential folded-cascode OTA using g_m/I_D methodology, and the sizing approach proposed by combining the SOS and the g_m/I_D technique are elaborated in Sect. 4. In Sect. 5, simulation results of the proposed method are included. Finally, Sect. 6 concludes the paper.

2 g_m/I_D sizing methodology

The g_m/I_D approach is one of the most prominent design methodologies to optimize the size of the transistors used in analog ICs [9, 25]. The g_m/I_D ratio becomes the key parameter for performing sizing for a specified I_D as defined [26]. Using g_m/I_D methodology circuit parameters can be optimized from three fundamental subplots. These fundamental subplots are obtained for a range of channel length (L) with respect to the transit frequency (f_T), self- gain (g_m/g_ds) (g_ds is the output conductance of a transistor) and current density (I_D/W). Characteristic plots of g_m/I_D technique in which the length of channel L changes from 0.18 µm to 2 µm in a 0.18 µm NMOS is shown in Fig. 1. In a similar manner, the results of PMOS transistors are also obtained.

Fig. 1

a Transit frequency (f_T). b Self-gain (g_m/g_ds). c Current density (I_D/W) changes with g_m/I_D(5-20S/A) with the length of channel L varies from 0.18 µm to 2 µm in a 0.18 µm NMOS transistor

The design flow using the g_m/I_D methodology is summarized below [10]:

• 1. For the given load capacitance C_L and Gain bandwidth product (GBW), the desired g_m can be calculated as.

  $$\mathop g\nolimits_{m} = GBW * \mathop C\nolimits_{L} = 2\varPi \mathop f\nolimits_{T} \mathop C\nolimits_{L}$$

  (1)

• 2. The drain current for the transistor is derived for a known g_m and designed value of g_m/I_D can be found out from self-gain (g_m/g_ds) versus g_m/I_D graph. It can be calculated as

  $$\mathop I\nolimits_{D} = \frac{{\mathop g\nolimits_{m} }}{{\left( {\frac{{\mathop g\nolimits_{m} }}{{\mathop I\nolimits_{D} }}} \right)}}$$

  (2)

• 3. The transistor channel width W can be calculated using the equation

  $$\mathop W = \frac{{\mathop I\nolimits_{D} }}{{\left( {\frac{{\mathop I\nolimits_{D} }}{{\mathop W\nolimits_{{}} }}} \right)}}$$

  (3)

where the denominator current density I_D/W can be defined from I_D/W versus g_m/I_D graph.

2.1 Noise which effects g_m/I_D analysis

2.1.1 Thermal noise

The thermal noise at the gate of a transistor is given by the following expression [27, 28]

$$\overline{{\mathop V\nolimits_{ng,th}^{2} }} = \frac{4kT\gamma }{{\mathop g\nolimits_{m} }} = \frac{4kT\gamma }{{\left( {\frac{{\mathop g\nolimits_{m} }}{{\mathop I\nolimits_{D} }}} \right)\mathop I\nolimits_{D} }}$$

(4)

where g_m is the transconductance, γ is the thermal noise coefficient which depends upon drain-to-source voltage (V_ds), the value of which is approximately 2/3 for long channel devices biased in the saturation region and k is the Boltzmann constant and T is the temperature in Kelvin.

2.1.2 Flicker noise

The flicker noise at the gate is given by following expression [27, 28]

$$\overline{{\mathop V\nolimits_{{\mathop {ng,fn}\nolimits_{{}} }}^{2} }} = \overline{{\mathop V\nolimits_{ng,th}^{2} }} \frac{{\mathop f\nolimits_{coner} }}{f}$$

(5)

where f_coner is the corner frequency which is a function of g_m/I_D,I_D/W and L as mention below.

$$\mathop f\nolimits_{corner} = \frac{{\mathop K\nolimits_{f} }}{{\mathop C\nolimits_{ox} L}}\frac{{\mathop g\nolimits_{m} }}{{\mathop I\nolimits_{D} }}\frac{{\mathop I\nolimits_{D} }}{W}\frac{1}{4kT\gamma }$$

(6)

The total noise present at the gate consists of the thermal noise and flicker noise which is equal to

$$\begin{aligned} \overline{{\mathop V\nolimits_{{\mathop {ng}\nolimits_{{}} }}^{2} }} = \overline{{\mathop V\nolimits_{ng,th}^{2} }} + \overline{{\mathop V\nolimits_{{\mathop {ng,fn}\nolimits_{{}} }}^{2} }} \hfill \\ \overline{{\mathop V\nolimits_{{\mathop {ng}\nolimits_{{}} }}^{2} }} = \frac{4kT\gamma }{{\left( {\frac{{\mathop g\nolimits_{m} }}{{\mathop I\nolimits_{D} }}} \right)\mathop I\nolimits_{D} }}\left( {1 + \frac{{\mathop f\nolimits_{corner} }}{f}} \right) \hfill \\ \end{aligned}$$

(7)

3 Computational approach of SOS

The optimization design problem of the analog circuit subject to some design constraints can be formulated as [24]

$$\left. \begin{aligned} {\text{Minimize}}:f(x) \hfill \\ {\text{Subject to}}:g(x) \le 0 \hfill \\ X_{L} < \, x \, < \, X_{H} . \hfill \\ \end{aligned} \right\}$$

(8)

where f(x) is the fitness function for minimization and g(x) is the non-linear inequality constraint. Vector x corresponds to the design variable set (x = [W_n,W_p]^T), and X_H, X_L are their upper and lower limits respectively. The constraints of the optimization problem as formulated in Eq. (8) can be solved using evolutionary algorithms. Here a population based algorithms optimization algorithm called SOS is proposed for this design as it is a superior optimization algorithm which overcomes the premature convergence and stagnation problem of the conventional optimisation algorithm. In the following subsections optimization of SOS techniques is discussed briefly which can be applied for the optimization.

3.1 Symbiotic organisms search algorithm (SOS)

In our ecosystem symbiotic interactions are observed between two organisms. This has inspired Cheng and Prayogo to develop SOS algorithm in 2014 [23]. The concept and overview of SOS algorithm is discussed in the following sub-sections.

3.2 Symbiosis: basic concept

In Greek ‘symbiosis’ means ‘living together’. The relationship between two different species of interdependent organisms was first defined in 1869 by German mycologist de Bary. The two types of Symbiotic relationships are obligate and facultative. Both organisms fully depend on each other in obligate relationship for their survival whereas in facultative relationship, it is not compulsory for the organisms to depend on each other [29, 30, 31].

In the nature we may find three types of symbiotic relationships. These are mutualism, commensalism and parasitism. When the relationships between two different species of organisms benefit each other, it is called Mutualism. When due to the relationship one get benefits and the other is not significantly affected it is called Commensalism and the kind of symbiotic relationship in which one organism is benefited and the other is harmed effectively is called Parasitism. For adopting themselves to the environment like improving their fitness level for long-term survival in the ecosystem, living organisms undergo symbiotic relationships.

3.3 Features of the SOS algorithm

Ecosystem is the initial population of organisms from where SOS algorithm originates. Here every organism is correlated to a fitness value for the ecosystem by considering it as a candidate solution to the corresponding problem such that degree of adaptation to the desired objective is imitated. In the ecosystem, by simulating the symbiotic interactions between two organisms through mutualism, commensalism and parasitism phases the new solutions are generated. Through these three phases every organism in the ecosystem interacts with the other randomly and the process is repeated until the criterion for termination is satisfied.

Following three subsections describe the phases of symbiotic relationship

3.3.1 Mutualism phase

In this phase of SOS algorithm both the organisms get benefitted from the interaction between them. In this phase, i^th and j^th organisms of the ecosystem are represented by Z_i and Z_j respectively. Let Z_j is a organism chosen randomly in the ecosystem which interacts with Z_j to create new candidate solutions as stated below.

$$\mathop Z\nolimits_{inew} = \mathop Z\nolimits_{i} + rand(0,1) \times (\mathop Z\nolimits^{best} - MV \times \mathop f\nolimits_{1} )$$

(9)

$$\mathop Z\nolimits_{jnew} = \mathop Z\nolimits_{j} + rand(0,1) \times (\mathop Z\nolimits^{best} - MV \times \mathop f\nolimits_{2} )$$

(10)

$${\text{where}}\;MV = \frac{{\mathop Z\nolimits_{i} + \mathop Z\nolimits_{j} }}{2}$$

(11)

and the rand (0, 1) is a random data between 0 and 1 which is uniformly generated. Also the randomly generated benefit factors are f₁ and f₂ which can be either 1 or 2 indicating the level of benefit to each organism. Here partial benefit is denoted by 1 and full benefit is denoted by 2. Average characteristics of organism Z_i and Z_j is termed as MV. The Z^best corresponds to an organism in the ecosystem with greatest degree of adaptation. If superior fitness function is provided as compared to the previous solutions, then new solutions can only be accepted.

3.3.2 Commensalism phase

It’s a type of symbiotic relationship between two organisms of different species in which one organism gains without harming the other one. Relationship between spider and the trees can be a good example in this regard where the spider gets benefit by creating nets on the tree and trapping the insects therein for food.However there is neither any benefit nor any affect to the tree due to spider activities.

To carry out the commensalism phase, from the ecosystem an organism Z_j is randomly selected for finding a relation between organism Z_i where in benefit is availed by organism Z_i without any benefit or harm to the organism Z_j from the relationship. So from the commensalism interaction, the new solution of Z_i can be generated as given by (12)

$$\mathop Z\nolimits_{inew} = \mathop Z\nolimits_{i} + rand( - 1,1) \times (\mathop Z\nolimits^{best} - \mathop Z\nolimits_{j} )$$

(12)

Here rand(−1,1) is a random number in between −1 and 1 which is uniformly generated and (Z^best− Z_j) defines the benefits availed by Z_i due to Z_j as a result of which, the organism Z_i can have a better survival in the ecosystem.

3.3.3 Parasitism phase

Effect of plasmodium parasites on human being is a simple example to demonstrate parasitic relationship. These parasites enter into the human body through the mosquitoes and propagate within the body as a result of which diseases like malaria may be caused leading to death.

In SOS algorithm for parasitism phase, mosquito is considered to be an organism Z_i. It generates Parasite_Vector which is nothing but an artificial parasite. Parasite_Vector is created by duplicating organism Z_i in the search space and then modifying the selected dimensions randomly using a random number. Organism Z_j selected from the ecosystem randomly serves as a host to the parasite vector. Z_j is then replaced by Parasite_Vector in the ecosystem. For measurement of their fitness, evaluation of both organisms are then carried out.If Parasite_Vector has a superior fitness value, it will kill organism Z_j and take its position where as Z_j will have immunity from the parasite and the Parasite_Vector die in that ecosystem in case the fitness value of Z_j is better than Parasite Vector.

3.4 Computing procedures for the analogue circuit design using SOS algorithm

The steps for the algorithm are outlined as follows.

Step 1 initialization of Ecosystem: Creation of initial population of the ecosystem is done followed by specifying control variables such as ecosystem size, maximum number of iterations etc. with the help of the design constraints. In the solution space, the positions of the organisms are represented by real numbers.

Step 2 Cost Function Evaluation (CF): Cost Function for each organism is evaluated for finding the best organism.

Step 3 Mutualism phase: Organisms are updated after mutual interaction between each other as a result of which the weaker organism is replaced by the better one.

Step 4 Commensalism phase: After performing the commensal interaction the organisms are updated with the one having better CF values.

Step 5 Parasitism phase: After generating the Parasite_Vector it is compared with random organism which then replaces the random organism, if the CF value produced by it is comparable to the random organism.

Step 6 Termination criterion: After reaching maximum number of iterations, the programme is terminated else it moves to Step 2.

4 Optimization of folded-cascode OTA circuit by combining SOS algorithm and g_m/I_D method

To verify the design accuracy and computational time of the g_m/I_D method with SOS algorithm, a low noise differential folded-cascode OTA circuit is analyzed using Cadence and MATLAB. A UMC 0.18 µm CMOS process is used for its implementation. Half circuit of the OTA has been considered for analysis as both the halves are assumed to be identical.For the differential folded-cascode OTA, the proposed optimization approach is detailed as below:

Step 1 Estimate the channel lengths L and the operation regions of transistors M₁–M₁₀ from the desired Gain (A_vd), transit frequencies f_T and Noise etc.

Step 2 Obtain the biasing conditions with an aim which guarantees that all transistors will be operating in the saturation region. So, it is necessary to take into account the biasing voltages, currents, (g_m)_1-10, and parasitic capacitances.

Step 3 Every (g_m/I_D)_1-10 value will yield a different g_m and a different g_ds which satisfies the DC gain requirement for the minimum channel length of transistors because of constant current.

Step 4 At every combination of (g_m/I_D)_1-10 and L_1-10 calculate the corresponding (I_D/W)_1-10. Considering the constraints (Gain (A_vd), Common mode rejection ratio (CMRR), gain bandwidth product (GBW), phase margin (PM), PSRR, power dissipation (P_diss) and Noise) determine the channel widths W_1-10 from I_D/W plot.

Step 5 Execute and run the SOS algorithm after the search space is reduced with the help of g_m/I_D method.

Step 6 During the optimization process define maximum and minimum values for each design variable along with design objectives, and constraints.

Step 7 For each iteration of SOS, corresponding transistor dimensions and bias voltages are calculated by considering the resulted values (obtained using g_m/I_D technique) for each particle.

Step 8 If the transistor sizes are within an allowed range under constraint conditions, then the cost function of the OTA is updated using SOS algorithm.

Step 9 Finally the noise performance results obtained from different process, voltage and temperature (PVT) variations of the differential folded-cascode OTA.

4.1 Design specifications of differential folded-cascode OTA circuit

Figure 2 shows the schematic diagram of differential folded-cascode OTA circuit [32, 33].A folded-cascode OTA is an important analog circuit because it provides large output voltage swing and less susceptible to common mode noise.The noise of the cascode configuration is contributed mostly by M_1-4 and M_9-10 as the effect of noise contributed by M_5-8 can be neglected. It requires a common mode feedback (CMFB) circuit with a bias current of 10µA to control the common–mode output voltage of the op-amp to a desirable fixed reference voltage, which is not shown in Fig. 2 to avoid circuit complexity.

Fig. 2

Schematic diagram of a differential folded-cascode OTA circuit

The design specificationsfor the OTA circuit arepresented in Table 1.

Table 1 Design specification of differential folded-cascode OTA

4.1.1 Design of the input pair M₁ and M₂

With the specifications of GBW and C_L as given in Table 1, the g_m of the input differential pair M₁ and M₂ can be obtained as 140μS using the formula GBW = g_m/2πC_L [32]. Since the 20μA bias current is divided equally between M₁ and M₂, the g_m/I_D of the input pair M₁ and M₂ can be found out as g_m/I_D1 ≈ 14 S/A.Thus, the self-gain of the M₁ and M₂ is calculated as g_m/g_ds1≥ 70 S/S (g_ds1= g_ds2< 2µS). According to the requirement, the maximum self-gain of transistor M₁ must be larger than 70 S/S. So, the channel length of transistor M₁ can be selected using the g_m/g_ds1 vs. g_m/I_D1 graph shown in Fig. 3(a). The lowest value of L₁ is equal to 0.6 μm chosen from Fig. 3(a) which gives g_m/g_ds1≈ 72S/S satisfying the gain requirement. Computation of the channel width W₁ is performed with the help of current density (I_D/W) vs. g_m/I_D graph shown in Fig. 3(b). To keep W₁ less than 50 µm, the minimum value of L₁ is selected as 0.8 µm. By taking the values for g_m/I_D1 and L₁ calculated previously current density can be ≈ 0.31 A/m. From this, the width can be calculated as W₁= I_D/(I_D/W) ≈ 34 µm.

Fig. 3

For input stage M₁ and M₂. a Self-gain (g_m/g_ds1). b Current density (I_D/W) when the length varies from 0.4 μm to 2 μm with an increment of 0.2μm. c The input-referred noise (spectral density) of M₁ as a function of g_m/I_D at frequency f = 100 kHz when the length of transistor M₁ is 0.8 μm

The input-referred noise is calculated to be 18nV/(Hz)^1/2 using L₁ = 0.8 µm and g_m/I_D1 = 15S/A as obtained in Fig. 3(c). This satisfies the design specification as listed in Table 1.

4.1.2 Design of load transistor M₃ and M₄

To explore the design space of the design variables the values of g_m/I_D3 and L₃ of M₃ and M₄ are set to a suitable value. According to Eq. (6), corner frequency f_corner varies inversely with L, which is dependent on the parameters g_m/I_D, I_D/W and γ of the transistor. For the long channel transistor, f_corner has to be minimized. With an increase in g_m/I_D, the current density decreases at a faster rate than the rate at which g_m/I_D increases due to γ considered to be a constant. Hence, f_corner decreases with the increase of g_m/I_D. It is therefore possible to reduce the input-referred noise by increasing g_m/I_D.

The selection of g_m/I_D3 of the load transistor is constrained by the corner frequency requirement and gain. The corner frequency f_corner3 should be less than 100 kHz to keep the input-referred noise voltage minimum as per the specification. Considering the f_corner3 requirement the minimum value of g_m/I_D3 is determined as shown in Fig. 4(a). It has been observed that the minimum value of g_m/I_D of transistor M₃ and M₄ is 7 S/A for L₃ = 1.4 μm. Initially, the range of g_m/I_D3 is fixed between 7 S/A ≤ g_m/I_D3≤ 20 S/A. From Fig. 4(b), it has been observed that the range of g_m/I_D3 that satisfies the gain requirement is g_m/I_D3 ≥ 11.5 S/A. With some margin, g_m/I_D3 = 12 S/A is used which satisfies the requirement.

Fig. 4

For load transistors (M₃ and M₄). a Corner frequency f_corner3. b Self-gain g_m/g_ds3. c Current density (I_D/W₃) changes with g_m/I_D3 = 5–20 S/A when L = 0.5 μm, 1.4 μm and 2 μm

The width of M₃ and M₄ can be calculated from the current density graph shown in Fig. 4(c). When L₃ = 1.4 μm the current density of M₃ and M₄ is I_D/W₃≈ 0.22A/m; thus W₃≈ 47 µm.

4.1.3 Design of cascode transistors M₅ and M₆

For the design of the transistor M₅ and M₆, the input-referred noise can be ignored because of its cascode configuration. The selection of g_m/I_D of the transistor M₅ and M₆ is constrained by the self-gain and width of transistors. To obtain the design variables let us consider g_m/I_D5 = 15 which results g_m = 150µS and g_m/g_ds5 ≥ 75 S/S. From the graph shown in Fig. 5(a), length of the channel for transistor M₅ that satisfies the gain requirement is L₅ = 0.6 µm and range of g_m/I_D5 should be 11≤ g_m/I_D5 ≤ 20S/A.

Fig. 5

For cascode transistors (M₅ and M₆). a Self-gain g_m/g_ds5 change with g_m/I_D5 = 5–20 S/A when L = 0.4 μm: 0.2 μm: 2 μm. b g_m/g_ds5change with L from (0–2 μm) when g_m/I_D5= 11, 13 and 20 S/A. c Current density (I_D/W₅) change with g_m/I_D5 = 5–20 S/A when L = 0.4 μm: 0.2 μm: 2 μm

From Fig. 5(b) it is seen that initially g_m/g_ds5 increases with an increase in channel length L₅ up to L₅ < 0.6 µm and remains constant for L₅ > 0.6 µm. Hence L₅ is set to 0.6 µm. To maximize gain and for obtaining the width as per specification g_m/I_D5 is set to be 13 S/A.

From Fig. 5(c) using g_m/I_D5 as 13 S/A and L₅= 0.6 µm the current density comes about ≈ 3.96 A/m which results W₅≈ 2.5 µm.

For the remaining PMOS transistors in folded cascode OTA circuit (Fig. 2), the methods described in Sects. 4.1.2 and 4.1.3 were used to find the design parameters which are summarized in Table 2. The OTA circuit netlist and specifications are imported into the MATLAB according to the design goals. Then the circuit simulator Cadence was invoked to perform the simulation.

Table 2 Summary of the differential folded- cascode OTA transistors sizing

4.2 Optimization approach by SOS

The performance parametersCMRR, PSRR, A_vd, GBW, PM, Noise, and P_diss formulated as design constraints and MOS transistor sizes (L and W) along with C_L are considered as design variables. These are provided within desired limits with the goal to minimize the area occupied by the individual circuit [32].

For the design of folded-cascode OTA circuit using SOS, the population matrix size for the particle vectors has been considered as (P × Q), where P = 80 and Q = 7. Numbers of particles in the population are indicated by row number (P) and the size of each particle vector (dimension) is indicated by the column number (Q). The particle vector in the population for the folded-cascode OTA circuit is defined as

$$X_{Folded - Cascode} = [CMRR, \, PSRR, \, A_{vd} , \, GBW, \, PM, \, Noise,P_{diss} ]$$

4.2.1 Constraints

• (a) Saturation conditions of the transistor: The transistors operate in the saturation mode when (g_m/I_D)_{0_10} = 10–20 S/A).

• (b) Design specification: Design specifications should satisfythe conditions mentioned in Table 1.

  $$Gain,\mathop A\nolimits_{vd} = \mathop g\nolimits_{m1} (\mathop r\nolimits_{out8} ||\mathop r\nolimits_{out6} )$$

  (13)
  $$\mathop A\nolimits_{vd} = \left( {\frac{{\mathop g\nolimits_{m} }}{{\mathop I\nolimits_{D} }}} \right)_{1} \mathop I\nolimits_{D1} (\mathop r\nolimits_{out8} ||\mathop r\nolimits_{out6} )$$

  (14)

  where r_out6 and r_out8 are the drain–source resistances of M₆ and M₈ respectively.

  $$GBW = \frac{{\mathop g\nolimits_{m1,2} }}{{\mathop C\nolimits_{L} }}$$

  (15)

• (c) Noise:

  $$\overline{{\mathop V\nolimits_{in,T}^{2} }} = \frac{8kT\gamma }{{\mathop I\nolimits_{D1} }}\left[ \begin{aligned} \frac{1}{{\mathop g\nolimits_{m1} }}\left( {1 + \frac{{\mathop f\nolimits_{corner1} }}{f}} \right) + \frac{1}{{\mathop g\nolimits_{m1} }}\left( {1 + \frac{{\mathop f\nolimits_{corner1} }}{f}} \right) + \hfill \\ \frac{1}{{\frac{{\mathop g\nolimits_{m3} }}{{\mathop I\nolimits_{D1} }}}}\left( {1 + \frac{{\mathop f\nolimits_{corner3} }}{f}} \right)\mathop {\left( {\frac{{\frac{{\mathop g\nolimits_{m3} }}{{\mathop I\nolimits_{D1} }}}}{{\frac{{\mathop g\nolimits_{m1} }}{{\mathop I\nolimits_{D1} }}}}} \right)}\nolimits^{2} + \hfill \\ \frac{1}{{\frac{{\mathop g\nolimits_{m9} }}{{\mathop I\nolimits_{D1} }}}}\left( {1 + \frac{{\mathop f\nolimits_{corner9} }}{f}} \right)\mathop {\left( {\frac{{\frac{{\mathop g\nolimits_{m9} }}{{\mathop I\nolimits_{D1} }}}}{{\frac{{\mathop g\nolimits_{m1} }}{{\mathop I\nolimits_{D1} }}}}} \right)}\nolimits^{2} \hfill \\ \end{aligned} \right]$$

  (16)

• (d) Design constraints: For the design parameters constraints can be set as C_L≥ 4.5pF, 0.18 µm ≤ L_i ≤ 2 µm and 2 µm ≤ W_i ≤ 50 µm for i = 1,2,…..10.

4.2.2 Cost function

The Cost Function (CF) is nothing but the total area occupied by the MOS transistors. This is equal to the multiplication of length and width of each transistor present in the OTA circuit as given below

$$\mathop {CF}\nolimits_{Folded - cascode} = \sum\nolimits_{i = 1}^{10} {\left( {\mathop {\mathop L\nolimits_{i} \times W}\nolimits_{i} } \right)}$$

(17)

To construct the OTA circuit, the number of transistors required for this design is 10. Here, the SOS algorithm was applied for optimization of the cost function CF_{Folded-Cascode.} The SOS algorithm has been executed with trial runs of 50 times for each circuit, and the best results have been reportedas indicated in the Fig. 10 below.

5 Simulation results

The proposed SOS optimization algorithm along with g_m/I_D method generated by MATLAB was implemented in Cadence for the optimal design of folded-cascode OTA circuit (Fig. 2). It was prominent that after getting the dimensions and the biasing voltages of the transistors using g_m/I_D technique from MATLAB, the SOS algorithm was programmed using MATLAB and Cadence was used to perform the simulation.

SOS algorithm along with g_m/I_D based simulation results of OTA circuit for typical conditions are presented in Figs. 6, 7, 8 and 9. The design of the folded-cascode OTA circuit using the proposed design technique satisfies all the design specifications. It is observed that least MOS area, better phase margin, higher gain, improved common mode rejection ratio, minimum power dissipation and noise has been obtained. So, this technique is the most appropriate for design and optimization of analog circuits.

Fig. 6

Simulated result of a gain versus frequency and b phase versus frequency of the folded-cascode OTA circuit

Fig. 7

Simulated CMRR response of folded-cascode OTA circuit

Fig. 8

Simulated noise response of folded-cascode OTA circuit

Fig. 9

Simulated result of PSRR for folded-cascode OTA

5.1 Convergence graph of proposed SOS

For the folded-cascode OTA, the convergence profile plot using SOS algorithm and SOS + g_m/I_D has been demonstrated in Fig. 10. The optimization was carried out for a population of 80 individuals and for 100 iterations.From Fig. 10, it is clear that to reach the optimal minimum values of total MOS area, the SOS approach needs 50 iterationsmeanwhile the SOS along with g_m/I_D takes only 30 iterations. To verify the robustness of the feasible solutions, comparative performance results of folded-cascode OTA obtained using the following algorithms i.e. GSA-PSO, GA, SOS and SOS with g_m/I_D are depicted in Table 3.

Fig. 10

Converging characteristics of cost function for the folded-cascode OTA circuit

Table 3 The comparative performance parameters of the proposed approach with GSA-PSO and GA

The comparative results of the proposed approach with the three benchmark algorithms over 50 independent runs in the form of box plots for the design of differential folded-cascade OTA circuit is shown in Fig. 11. The comparative statistical results of the proposed approach with SOS algorithm for the OTA circuit are given in Table 4. It is observed that, lower mean and standard deviation value for the proposed method is very small which justifies the accuracy of proposed methodology.

Fig. 11

Box plot representing the comparison of proposed approach with GSA-PSO, GA, SOS and SOS + g_m/I_D obtained after 50 independent runs for design of differential folded-cascode OTA

Table 4 Statistical performances results over 50 runs of SOS algorithm and SOS algorithm along with g_m/I_D

The noise performance results obtained using different PVT variations of the folded-cascode OTA are shown in Fig. 12. From the corner analysis plots, it is observed that, the process corners and voltages are resulting small noise variations than the temperature corner simulations. However, for all process corner cases except slow–slow (SS) the proposed design closely meets the specifications.

Fig. 12

Variation in the input referred noise with a process corners, b voltage corners, c temperature corners

The computational time and error between SOS and SOS with g_m/I_D are given by Table 5. For the first case, the execution time is 29.63 s for 100 fitness evaluations, while the execution time for reaching the minimum value with the proposed approach is 8.59 s.

Table 5 Comparison of the computational time and error between SOS alone and SOS with g_m/I_D for the design of folded-cascode OTA

In addition to this, the error which can be defined as the deviation between the final value and the target value is obtained as < 8% in this paper. In short, it can be stated that the proposed method not only enhances the design speed but also improves the accuracy of the circuit design. So, the g_m/I_D methodology with SOS algorithm is a better optimizer for the design of the low-noise folded-cascode OTA circuit.

6 Conclusions

In this paper, SOS algorithm along with g_m/I_D method is employed for the optimal design of differential folded-cascode OTA circuit. From the simulation results, it is clearly seen that using our proposed optimisation approach, convergences can be achieved in less number of iterations than SOS alone. So the g_m/I_D technique is quite useful in reducing computational time for optimizing the sizes of the transistors along with evolutionary algorithm. It has been observed that, the design of folded-cascode OTA circuit using this optimisation approach and PVT analysis not only met all design specifications but also minimized the total gate area, noise and the power dissipation. The computed feasible solutions after applying our proposed approach are found to be quite robust to PVT variations also. Thus, in comparison with other optimization techniques, this method can be used to save computational time, reduce error and optimize the size of transistors.