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Fast Quantum-Dot Cellular Automata Adder/Subtractor Using Novel Fault Tolerant Exclusive-or Gate and Full Adder

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Abstract

Quantum-dot Cellular automata is a promising area to implement digital systems at nano scale level. Adders and subtractors are widely used in almost every digital information processing system. This work targets to design an efficient 8-bit adder/subtractor that can perform addition as well as subtraction by using a novel control signal distribution scheme. To perform controlled inversion of inputs a novel exclusive-or gate with fewer cells is proposed. During Quantum-dot Cellular automata circuit fabrication, missing cell defects have the potential to affect the performance of a circuit. The proposed designs have higher fault resistance to missing cell defects compared to the existing state-of-the-art designs. Results demonstrate that the proposed design has (N-2) less clock phases compared to the existing state-of-the-art designs. The proposed design can be extended to implement any N-bit adder/subtractor. All the designs are designed and verified using coherence vector simulation engine in QCADesigner.

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Authors and Affiliations

  1. Department of Electronics and Communication Engineering, National Institute of Technology, Tiruchirappalli, 620015, India

    Marshal Raj & Lakshminarayanan Gopalakrishnan

  2. Department of Electrical and Computer Engineering, University of Saskatchewan, Saskatoon, Canada

    Seok-Bum Ko

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  1. Marshal Raj
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  2. Lakshminarayanan Gopalakrishnan
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Correspondence to Marshal Raj.

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Raj, M., Gopalakrishnan, L. & Ko, SB. Fast Quantum-Dot Cellular Automata Adder/Subtractor Using Novel Fault Tolerant Exclusive-or Gate and Full Adder. Int J Theor Phys 58, 3049–3064 (2019). https://doi.org/10.1007/s10773-019-04184-7

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