Skip to main content
SpringerLink
Log in

Transistor level SCA-resistant scheme based on fluctuating power logic

  • Letter
  • Published:
Science China Information Sciences Aims and scope Submit manuscript

This is a preview of subscription content, log in via an institution to check access.

Access this article

Log in via an institution

Price excludes VAT (USA)
Tax calculation will be finalised during checkout.

Instant access to the full article PDF.

Institutional subscriptions

References

  1. Saravanan P, Kalpana P. An energy efficient XOR gate implementation resistant to power analysis attacks. J Eng Sci Tech, 2015, 10: 1275–1292

    Google Scholar 

  2. Mangard S, Oswald E, Popp T. Power Analysis Attacks: Revealing the Secrets of Smart Cards. Berlin: Springer Science & Business Media,2008

    MATH  Google Scholar 

  3. Moradi A, Kirschbaum M, Eisenbarth T, et al. Masked dual-rail precharge logic encounters state-ofthe-art power analysis methods. IEEE Trans Very Large Scale Integr Syst, 2012, 20: 1578–1589

    Article  Google Scholar 

  4. Kawaguchi H, Sakurai T. A reduced clock-swing flipflop (RCSFF) for 63% power reduction. IEEE J Solid- State Circ, 1998, 33: 807–811

    Article  Google Scholar 

  5. Zhao P, Darwish T, Bayoumi M. High-performance and low power conditional discharge flip-flop. IEEE Trans Very Large Scale Integr Syst, 2004, 12: 477–484

    Article  Google Scholar 

Download references

Acknowledgements

This work was supported in part by National Natural Science Foundation of China (Grant Nos. 61173191, 61272491, 61309021, 61472357, 61571063), National Basic Research Program of China (973 Program) (Grant No. 2013CB338004), and Science and Technology on Communication Security Laboratory (Grant No. 9140C110602150C11053).

Author information

Authors and Affiliations

  1. College of Information Science and Electronic Engineering, Zhejiang University, Hangzhou, 310027, China

    Liang Geng, Fan Zhang & Jizhong Shen

  2. Science and Technology on Communication Security Laboratory, Chengdu, 610041, China

    Fan Zhang

  3. Temasek Laboratories, Nanyang Technological University, Singapore, 637371, Singapore

    Wei He & Shivam Bhasin

  4. The Institute of North Electronic Equipment, Beijing, 100191, China

    Xinjie Zhao & Shize Guo

Authors
  1. Liang Geng
    View author publications

    You can also search for this author in PubMed Google Scholar

  2. Fan Zhang
    View author publications

    You can also search for this author in PubMed Google Scholar

  3. Jizhong Shen
    View author publications

    You can also search for this author in PubMed Google Scholar

  4. Wei He
    View author publications

    You can also search for this author in PubMed Google Scholar

  5. Shivam Bhasin
    View author publications

    You can also search for this author in PubMed Google Scholar

  6. Xinjie Zhao
    View author publications

    You can also search for this author in PubMed Google Scholar

  7. Shize Guo
    View author publications

    You can also search for this author in PubMed Google Scholar

Corresponding author

Correspondence to Fan Zhang.

Additional information

The authors declare that they have no conflict of interest.

Electronic supplementary material

Rights and permissions

Reprints and permissions

About this article

Check for updates. Verify currency and authenticity via CrossMark

Cite this article

Geng, L., Zhang, F., Shen, J. et al. Transistor level SCA-resistant scheme based on fluctuating power logic. Sci. China Inf. Sci. 60, 109401 (2017). https://doi.org/10.1007/s11432-016-9046-4

Download citation

  • Received:

  • Accepted:

  • Published:

  • DOI: https://doi.org/10.1007/s11432-016-9046-4

Search

Navigation