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Ultimate dielectric scaling of 2D transistors via van der Waals metal integration

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Abstract

The two-dimensional transition metal dichalcogenides (TMDs) have attracted intense interest as an atomically thin semiconductor channel for the continued transistor scaling. However, with a dangling bond free surface, it has been a key challenge to reliably integrate high-quality gate dielectrics on TMDs. In particular, the atomic layer deposition of dielectrics on TMDs typically features highly non-uniform nucleation and produces a highly rough or porous dielectric film with rich pinholes that are prone to further damage during the gate integration process. Herein we report a van der Waals (vdW) integration route towards highly reliable gate metal integration on porous dielectrics. The physical lamination process employed by the vdW integration avoids the direct deposition of metal electrodes into porous dielectrics to ensure reliable gate integration and produce low gate leakage devices. The electrical measurements demonstrate the vdW integrated MoS2 top gate devices exhibit substantially reduced gate leakage current that is about 3–5 orders of magnitude smaller than that with deposited metal electrodes. Furthermore, we show the vdW integration process can be used to create high performance top-gated MoS2 transistors with ultrathin Al2O3 dielectrics down to 1 nm, representing the ultimate dielectric scaling for TMDs transistors. This study demonstrates that vdW integration can enable highly reliable gate integration on relatively low quality dielectrics on TMDs, and opens an interesting pathway to high-performance top-gate transistors using dangling bond free two-dimensional (2D) semiconductors.

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Acknowledgements

Y. L. acknowledges the financial support from the National Key R&D Program of China (No. 2018YFA0703700) and the National Natural Science Foundation of China (Nos. 51802090, 61874041, 51991340, and 51991341). X. D. acknowledges the support from the National Natural Science Foundation of China (No. 51991343). W. D. thanks Gonglei Shao and Hang Liu for AFM measurement, Liqiang Zhang and Xiaohua Shen for modifying the format of the paper, and Weisheng Li, Guanhua Yang, Yang Liu and Zhong Wan for the technique support of dual-gate measurement.

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Authors and Affiliations

  1. Hunan Key Laboratory of Two-Dimensional Materials and State Key Laboratory for Chemo/Biosensing and Chemometrics, College of Chemistry and Chemical Engineering, Hunan University, Changsha, 410082, China

    Weiqi Dang, Bei Zhao, Xiangdong Yang, Bo Li, Jia Li, Hongmei Zhang, Ziyue Qin & Xidong Duan

  2. Hunan Key Laboratory of Two-Dimensional Materials, Department of Applied Physics, School of Physics and Electronics, Hunan University, Changsha, 410082, China

    Lingan Kong, Zheyi Lu, Bo Li, Wanying Li, Shun Shi & Yuan Liu

  3. Laboratory for Micro/Nano Optoelectronic Devices of Ministry of Education & Hunan Provincial Key Laboratory of Low-Dimensional Structural Physics and Devices, School of Physics and Electronics, Hunan University, Changsha, 410082, China

    Chang Liu & Lei Liao

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  1. Weiqi Dang
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  2. Bei Zhao
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  3. Chang Liu
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  4. Xiangdong Yang
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  7. Bo Li
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  14. Xidong Duan
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  15. Yuan Liu
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Correspondence to Xidong Duan or Yuan Liu.

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Dang, W., Zhao, B., Liu, C. et al. Ultimate dielectric scaling of 2D transistors via van der Waals metal integration. Nano Res. 15, 1603–1608 (2022). https://doi.org/10.1007/s12274-021-3708-1

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  • DOI: https://doi.org/10.1007/s12274-021-3708-1

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