Abstract
In this letter, a planar integration using the deep trench isolation (DTI) technique is proposed to suppress the inter-well parasites in smart power integrated circuits implemented in 0.35 µm BiCMOS technology. In this technology, all devices share the same epitaxial layer. This can lead to a punch-through between power devices as well as between power and low-voltage CMOS devices. A DTI scheme is used to suppress the effect of the parasitic BJT by using a P+ retardation implant region under the deep trench isolation region. The injection ratio of the parasitic BJT is reduced by a factor between 3 and 8.5. The effect of the trench length and the retardation implant is investigated using SENTAURUS TCAD simulations. It is confirmed, through using TCAD simulations, that the amount of the collected carriers of the sensitive devices changes as a function of the trench length and the presence of the retardation implant.
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References
Khemka V, Zhu R, Bose A, Roggenbauer T (2007) Optimization and elimination of parasitic latchup in advanced smart-power technologies. IEEE Trans Dev Mater Reliab 7(1):69–73
Lo Conte F, Sallese JM, Pastre M, Krummenacher F, Kayal M (2010) Global modeling strategy of parasitic coupled currents induced by minority-carrier propagation in semiconductor substrates. IEEE Trans Electron Dev 57(1):263–272
Stefanucci C, Buccella P, Kayal M, Sallese JM (2015) Spice-compatible modeling of high injection and propagation of minority carriers in the substrate of Smart Power ICs. Solid State Electron 105:21–29
Chan WWT, Sin JKO, Wong SS (1998) A novel crosstalk isolation structure for bulk CMOS power IC’s. IEEE Trans Electron Dev 45(7):1580–1586
Gupta S, Beckman JC, Kosier SL (2001) Unbiased guard ring for latchup-resistant, junction-isolated smart-power ICs. In: IEEE Proc BCTM, pp 188–191
Parthasarathy V, Zhu R, Khemka V, Roggenbauer T, Bose A, Hui P, Rodriquez P, Nivison J, Collins D, Wu Z, Puchades I, Butner M (2002) A 0.25 µm CMOS based 70 V smart power technology with deep trench for high- voltage isolation. In: Proc. IEDM, pp 459–462
Ferrari R, Morelli NM (1991) New levels of integration in automotive electronics. In: International symposium on vehicle electronics integration, pp 187–201
Wolf S (2002) Silicon processing for the VLSI era. Lattice Press, Sunset Beach
Berberich SE, Bauer AJ, Frey L, Ryssell H (2003) Trench sidewall doping for lateral power devices. In: IEEE proc of ESSDERC, pp 379–382
Valorge O, Sun F, Lorival JE, Abouelatta-Ebrahim M, Calmon F, Gontrand C (2012) Analytical and numerical model confrontation for transfer impedance extraction in three-dimensional radio frequency circuits. Circuits Syst 3(2):126–135
Abouelatta-Ebrahim M, Shaker A, Sayah GT, Gontrand C, Zekry A (2015) Design considerations of high voltage RESURF nLDMOS: an analytical and numerical study. Ain Shams Eng J 6(2):501–509
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The authors are thankful to the UpM (Union pour la Méditerranéenne) for the collaboration and joint research work.
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Abouelatta, M., Salem, M.S., Shaker, A. et al. Parasitic Suppression in 2D Smart Power ICs Using Deep Trench Isolation: A Simulation Study. Natl. Acad. Sci. Lett. 43, 167–170 (2020). https://doi.org/10.1007/s40009-019-00830-0
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DOI: https://doi.org/10.1007/s40009-019-00830-0