Improving the Performance of a Multibit Arithmetic Logic Unit

Abstract

In modern microprocessors, the arithmetic logic units (ALUs) with the accelerated transfer organization, which are faster than ALUs with the sequential organization of arithmetic transfer, are widely used to reduce time costs. However, as the input data capacity increases, the operating time of such ALUs increases linearly with an increase in the number of bits. Developing an efficient ALU to deliver better performance than the existing known solutions is a pressing challenge. In this study, ALUs with the sequential and accelerated organization of arithmetic transfer are analyzed. A multidigit ALU is developed to increase the operating speed. All the ALU schemes were modeled in the CAD Altera Quartus-II environment. The number of gates and the maximum delay in the ALU circuit simulation report are compared for 4, 8, 16, 32, and 64 bits. A results verification scheme is implemented to confirm the reliability of the developed ALU. It is found that when performing operations with 64-bit operands, the developed ALU reduces the maximum delay by 53% compared to ALUs with the sequential organization of the arithmetic transfer and by 35.5% compared to ALUs with the accelerated organization of the arithmetic transfer.