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Charge Transport in Pentacene Thin Film Transistors

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Abstract

The charge transport properties in polycrystalline pentacene thin film transistors is investigated. A potential barrier is formed at grain boundaries due charged trapping states. The influence of such grain boundaries on the hole mobility of the devices is analyzed for different grain sizes, trap concentrations, and carrier densities. The results reveal that room temperature mobilities exceeding 0.5 cm2/Vs can be obtained in thin films with large grains as well as in nanocrystalline material. Consequently, single crystal device limits can be reached also by polycrystalline pentacene thin film transistors.

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Authors and Affiliations

  1. Bell Laboratories, Lucent Technologies, 600 Mountain Ave., Murray Hill, NJ, 07974, USA

    J. H. Schön, L. D. Buchholz & Ch Kloc

  2. Solid State Physics Laboratory, ETH Hönggerberg, CH-8093, Zürich, Switzerland

    B. Batlogg

Authors
  1. J. H. Schön
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  2. L. D. Buchholz
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  3. Ch Kloc
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  4. B. Batlogg
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Schön, J.H., Buchholz, L.D., Kloc, C. et al. Charge Transport in Pentacene Thin Film Transistors. MRS Online Proceedings Library 665, 533 (2000). https://doi.org/10.1557/PROC-665-C5.33

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  • DOI: https://doi.org/10.1557/PROC-665-C5.33

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