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A method for synthesis of easily-testable circuits in some basis admitting single fault detection tests of constant length

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Abstract

A method of synthesis of irredundant circuits of functional elements in the basis {x&y, x⊕y, 1, \(\bar x\)(y ∨ z) ∨ x(y ∼ z)} realizing arbitrary Boolean functions and admitting unit verification tests of the length not exceeding 4 is proposed in the paper for inverse or constant (stuck-at) faults at outputs of gates.

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References

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Authors and Affiliations

  1. Faculty of Computational Mathematics and Cybernetics, Moscow State University, Leninskie Gory, Moscow, 119991, Russia

    D. S. Romanov

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  1. D. S. Romanov
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Original Russian Text © D.S. Romanov, 2012, published in Vestnik Moskovskogo Universiteta, Matematika. Mekhanika, 2012, Vol. 67, No. 2, pp. 24–29.

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Romanov, D.S. A method for synthesis of easily-testable circuits in some basis admitting single fault detection tests of constant length. Moscow Univ. Math. Bull. 67, 69–73 (2012). https://doi.org/10.3103/S0027132212020064

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  • DOI: https://doi.org/10.3103/S0027132212020064

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