Overview
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Table of contents (11 chapters)
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Front Matter
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Introduction
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Design of VLSI Circuits
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RISC Architectures
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Short Introduction to VERILOG
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External Specification of Behavior
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Internal Specification of Coarse Structure
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Pipeline of the Coarse Structure Model
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Synthesis of Gate Model
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Testing, Testability, Tester, and Testboard
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Summary and Prospect
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HDL Models for Circuits and Architectures
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Front Matter
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Back Matter
Keywords
About this book
After emphasizing the economic importance of chip design as a key technology, the book deals with VLSI design (Very Large Scale Integration), the design of modern RISC processors, the hardware description language VERILOG, and typical modeling techniques. Numerous examples as well as a VERILOG training simulator are included on a disk.
Authors and Affiliations
Bibliographic Information
Book Title: VLSI Chip Design with the Hardware Description Language VERILOG
Book Subtitle: An Introduction Based on a Large RISC Processor Design
Authors: Ulrich Golze
DOI: https://doi.org/10.1007/978-3-642-61001-1
Publisher: Springer Berlin, Heidelberg
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eBook Packages: Springer Book Archive
Copyright Information: Springer-Verlag Berlin Heidelberg 1996
Softcover ISBN: 978-3-642-64650-8Published: 23 August 2014
eBook ISBN: 978-3-642-61001-1Published: 11 November 2013
Edition Number: 1
Number of Pages: XIV, 360
Number of Illustrations: 37 b/w illustrations
Topics: Logic Design, Electronics and Microelectronics, Instrumentation