Skip to main content

Nanoelectronics and Hardware Security

  • Chapter
  • First Online:
Network Science and Cybersecurity

Abstract

In recent years, the field of nanoelectronics has yielded several nanoscale device families that exhibit the high device densities and energy-efficient operation required for emerging integrated circuit applications. For example, the memristor (or “memory resistor”) is a two-terminal nanoelectronic switch particularly well suited for applications such as high-density reconfigurable computing and neuromorphic hardware. In addition to increased device densities and energy-efficient operation, nanoelectronic systems are also subject to a high degree of variability, often seen as a negative for conventional circuit designs. However, in terms of implementing certain security primitives, variability is a feature that can be harnessed to improve security and trust in integrated circuits. The focus of this chapter is the utilization of nanoelectronic hardware for improved hardware security in emerging nanoelectronic and hybrid CMOS-nanoelectronic processors. Specifically, features such as variability and low power dissipation can be harnessed for side-channel attack mitigation, improved encryption/decryption and anti-tamper design. Furthermore, the novel behavior of nanoelectronic devices can be harnessed for novel computer architectures that are naturally immune to many conventional cyber attacks. For example, chaos computing utilizes chaotic oscillators in the hardware implementation of a computing system such that operations are inherently chaotic and thus difficult to decipher.

The material and results presented in this paper have been cleared for public release, unlimited distribution by AFRL, case number 88ABW-2013-0830. Any opinions, findings and conclusions or recommendations expressed in this material are those of the authors and do not necessarily reflect the views of AFRL or its contractors.

This is a preview of subscription content, log in via an institution to check access.

Access this chapter

Chapter
USD 29.95
Price excludes VAT (USA)
  • Available as PDF
  • Read on any device
  • Instant download
  • Own it forever
eBook
USD 39.99
Price excludes VAT (USA)
  • Available as EPUB and PDF
  • Read on any device
  • Instant download
  • Own it forever
Softcover Book
USD 54.99
Price excludes VAT (USA)
  • Compact, lightweight edition
  • Dispatched in 3 to 5 business days
  • Free shipping worldwide - see info
Hardcover Book
USD 54.99
Price excludes VAT (USA)
  • Durable hardcover edition
  • Dispatched in 3 to 5 business days
  • Free shipping worldwide - see info

Tax calculation will be finalised at checkout

Purchases are for personal use only

Institutional subscriptions

References

  1. Inquiry into counterfeit electronic parts in the department of defense supply chain, in Report 112-167, Committee on Armed Services, 112th Congress, 2nd Session (United States Senate, U.S. Government Printing Office, Washington, DC, 2012)

    Google Scholar 

  2. Y. Alkabani, F. Koushanfar, Active control and digital rights management of integrated circuit IP cores, in Proceedings of the IEEE International Conference on Compilers, Architectures and Synthesis for Embedded Systems, 2008, pp. 227–234

    Google Scholar 

  3. J. Guajardo, S. Kumar, G.-J. Schrijen, P. Tuyls, Physical unclonable functions and public-key crypto for FPGA IP protection, in Proceedings of the IEEE International Conference on Field Programmable Logic and Applications, 2007, pp. 189–195

    Google Scholar 

  4. G.E. Suh, C.W. O’Donnell, I. Sachdev, S. Devadas, Design and implementation of the AEGIS single-chip secure processor using physical random functions, in Proceedings of IEEE/ACM International Conference on Computer Architecture, (2005), pp. 25–36

    Google Scholar 

  5. P. Kocher, J. Jaffe, J. Benjamin, Differential Power Analysis, Advances in Cryptology—CRYPTO’99 (Springer, Berlin, 1999)

    Google Scholar 

  6. P. Kocher, Timing Attacks on Implementations of Diffie-Hellman, RSA, DSS, and Other Systems, Advances in Cryptology—CRYPTO’96 (Springer, Berlin, 1996)

    Google Scholar 

  7. D. Agrawal, B. Archambeault, J. Rao, P. Rohatgi, The EM side—channel (s). Cryptogr. Hardw. Embed. Syst. CHES 2002, 29–45 (2002)

    Google Scholar 

  8. J.-J. Quisquater, D. Samyde, Electromagnetic analysis (ema): measures and counter-measures for smart cards, in Smart Card Programming and Security (2001), pp. 200–210

    Google Scholar 

  9. F.-X. Standaert, Introduction to side-channel attacks, in Secure Integrated Circuits and Systems (2010), pp. 27–42

    Google Scholar 

  10. K. Tiri, Side-channel attack pitfalls, in ACM/IEEE 44th Design Automation Conference, 2007 (DAC’07) (IEEE, 2007), pp. 15–20

    Google Scholar 

  11. D. Agrawal, R. Josyula, R. Pankaj, Multi-channel attacks. in Cryptographic Hardware and Embedded Systems-CHES 2003, pp. 2–16

    Google Scholar 

  12. E. Brier, C. Clavier, F. Olivier, Optimal statistical power analysis (2003), http://eprint.iacr.org/2003/152

  13. E. Brier, C. Clavier, F. Olivier, Correlation power analysis with a leakage model, in Cryptographic Hardware and Embedded Systems-CHES 2004 (2004), pp. 135–152

    Google Scholar 

  14. C. Clavier, J.-S. Coron, N. Dabbous, Differential power analysis in the presence of hardware countermeasures, in Cryptographic Hardware and Embedded SystemsCHES 2000 (Springer, Berlin, 2000), pp. 13–48

    Google Scholar 

  15. S. Chari, C. Jutla, J. Rao, P. Rohatgi, Towards sound approaches to counteract power-analysis attacks, in Advances in CryptologyCRYPTO’99 (Springer Berlin, 1999), pp. 791–791

    Google Scholar 

  16. J.A. Ambrose, G.R. Roshan, S. Parameswaran, RIJID: random code injection to mask power analysis based side channel attacks, in DAC’07. ACM/IEEE 44th Design Automation Conference, 2007 (IEEE, 2007)

    Google Scholar 

  17. J.A. Ambrose, S. Parameswaran, A. Ignjatovic, MUTE-AES: a multiprocessor architecture to prevent power analysis based side channel attack of the AES algorithm, in Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design (IEEE Press, 2008)

    Google Scholar 

  18. S. Guilley, P. Hoogvorst, R. Pacalet, Differential power analysis model and some results, in Smart Card Research and Advanced Applications Vi (2004), pp. 127–142

    Google Scholar 

  19. K. Tiri, D. Hwang, A. Hodjat, B. Lai, S. Yang, P. Schaumont, I. Verbauwhede, A side-channel leakage free coprocessor IC in 0.18 μm CMOS for embedded AES-based cryptographic and biometric processing, in Proceedings of the 42nd Design Automation Conference, 2005 (IEEE, 2005), pp. 222–227

    Google Scholar 

  20. C. Tokunaga, D. Blaauw, Securing encryption systems with a switched capacitor current equalizer. Solid State Circ. IEEE J. 45(1), 23–31 (2010)

    Article  Google Scholar 

  21. J.-W. Lee, S.-C. Chung, H.-C. Chang, C.-Y. Lee, An efficient countermeasure against correlation power-analysis attacks with randomized montgomery operations for DF-ECC processor, in Cryptographic Hardware and Embedded SystemsCHES 2012, pp. 548–564

    Google Scholar 

  22. T. Popp, S. Mangard, Masked dual-rail pre-charge logic: DPA-resistance without routing constraints, in Cryptographic Hardware and Embedded SystemsCHES 2005, pp. 172–186

    Google Scholar 

  23. J. Blömer, J. Guajardo, V. Krummel, Provably Secure Masking of AES, Selected Areas in Cryptography (Springer, Berlin, 2005)

    Google Scholar 

  24. R. Muresan, C. Gebotys, Current flattening in software and hardware for security applications, in International Conference on Hardware/Software Codesign and System Synthesis, 2004. CODES + ISSS 2004 (IEEE, 2004)

    Google Scholar 

  25. H. Vahedi, R. Muresan, S. Gregori, On-chip current flattening circuit with dynamic voltage scaling, in Proceedings of 2006 IEEE International Symposium on Circuits and Systems, 2006. ISCAS 2006 (IEEE, 2006)

    Google Scholar 

  26. D. May, H.L. Muller, N. Smart, Non-deterministic processors, in Information Security and Privacy (Springer, Berlin, 2001)

    Google Scholar 

  27. J. Irwin, D. Page, N.P. Smart, Instruction stream mutation for non-deterministic processors, in Proceedings of the IEEE International Conference on Application-Specific Systems, Architectures and Processors, 2002 (IEEE, 2002)

    Google Scholar 

  28. B.D. Briggs, S.M. Bishop, K.D. Leedy, B. Butcher, R.L. Moore, S.W. Novak, N.C. Cady, Influence of copper on the switching properties of hafnium oxide-based resistive memory, in MRS Proceedings, vol. 1337, 2011

    Google Scholar 

  29. L. Goux, J.G. Lisoni, M. Jurczak, D.J. Wouters, L. Courtade, Ch. Muller, Coexistence of the bipolar and unipolar resistive-switching modes in NiO cells made by thermal oxidation of Ni layers. J. Appl. Phys. 107(2), 024512–024512-7 (2010)

    Article  Google Scholar 

  30. A. Sawa, T. Fujii, M. Kawasaki, Y. Tokura, Interfaces resistance switching at a few nanometer thick perovskite manganite layers. Appl. Phys. Lett. 88(23), 232112–232112-3 (2006)

    Article  Google Scholar 

  31. K. Szot, W. Speier, G. Bihlmayer, R. Waser, Switching the electrical resistance of individual dislocations in single crystalline SrTiO3. Nat. Mat. 5, 312–320 (2006)

    Article  Google Scholar 

  32. J.C. Scott, L.D. Bozano, Nonvolatile memory elements based on organic materials. Adv. Mat. 19, 1452–1463 (2007)

    Article  Google Scholar 

  33. N.B. Zhitenev, A. Sidorenko, D.M. Tennant, R.A. Cirelli, Chemical modification of the electronic conducting states in polymer nanodevices. Nat. Nanotech. 2, 237–242 (2007)

    Article  Google Scholar 

  34. M. Di Ventra, Y.V. Pershin, L.O. Chua, Circuit elements with memory: memristors, memcapacitors, and meminductors. Proc. IEEE 97, 1717–1724 (2009)

    Article  Google Scholar 

  35. D.B. Strukov, G.S. Snider, D.R. Stewart, R.S. Williams, How we found the missing memristor. Nature 453, 80–83 (2008)

    Article  Google Scholar 

  36. L.O. Chua, Memristor-the missing circuit element. IEEE Trans. Circ. Theory ct-18(5), 507–519 (1971)

    Article  Google Scholar 

  37. L.O. Chua, S.M. Kang, Memrisive devices and systems. Proc. IEEE 64(2), 209–223 (1976)

    Article  MathSciNet  Google Scholar 

  38. J.P. Strachan, D.B. Strukov, J. Borghetti, J.J. Yang, G. Medeiros-Ribeiro, R.S. Williams, The switching location of a bipolar memristor: chemical, thermal and structural mapping. Nanotechnology 22(25), 254015 (2011)

    Article  Google Scholar 

  39. Y. Joglekar, S. Wolf, The elusive memristor: properties of basic electrical circuits. Eur. J. Phys. 30, 661–675 (2009)

    Article  MATH  Google Scholar 

  40. G.S. Rose, H. Manem, J. Rajendran, R. Karri, R. Pino, Leveraging memristive systems in the constructure of digital logic circuits and architectures. Proc. IEEE 100(6), (2012),pp. 2033–2049

    Google Scholar 

  41. J. Rajendran, H. Manem, R. Karri, G.S. Rose, Approach to tolerate process related variations in memristor-based applications, in International Conference on VLSI Design (2011), pp. 18–23

    Google Scholar 

  42. N.R. McDonald, Al/Cu x O/Cu Memristive Devices: Fabrication, Characterization, and Modeling, M.S., College of Nanoscale Science and Engineering University at Albany, SUNY, Albany, NY, 2012, 1517153

    Google Scholar 

  43. A.S. Oblea, A. Timilsina, D. Moore, K.A. Campbell, Silver chalcogenide based memristor devices, in The 2010 International Joint Conference on Neural Networks (IJCNN), 18–23 July 2010, pp. 1–3

    Google Scholar 

  44. Q.F. Xia, W. Robinett, M.W. Cumbie, N. Banerjee, T.J. Cardinali, J.J. Yang, W. Wu, X.M. Li, W.M. Tong, D.B. Strukov, G.S. Snider, G. Medeiros-Ribeiro, R.S. Williams, Memristor − CMOS hybrid integrated circuits for reconfigurable logic. Nano Lett. 9, 3640 (2009)

    Article  Google Scholar 

  45. H. Manem, G.S. Rose, A read-monitored write circuit for 1T1M memristor memories, in Proceedings of IEEE International Symposium on Circuits and Systems (Rio de Janeiro, Brazil, 2011)

    Google Scholar 

  46. H. Manem, J. Rajendran, G.S. Rose, Design considerations for multi-level CMOS/nano memristive memory. ACM J. Emerg. Technol. Comput. Syst. 8(1), 6:1–22 (2012)

    Google Scholar 

  47. G.S. Rose, Y. Yao, J.M. Tour, A.C. Cabe, N. Gergel-Hackett, N. Majumdar, J.C. Bean, L.R. Harriott, M.R. Stan, Designing CMOS/molecular memories while considering device parameter variations. ACM J. Emerg. Technol. Comput. Syst. 3(1), 3:1–24 (2007)

    Google Scholar 

  48. J. Rajendran, R. Karri, J.B. Wendt, M. Potkonjak, N. McDonald, G.S. Rose, B. Wysocki, Nanoelectronic solutions for hardware security (2012), http://eprint.iacr.org/2012/575

  49. B. Gassend, D. Clarke, M. van Dijk, S. Devadas, Silicon physical random functions, in Proceedings of the ACM International Conference on Computer and Communications Security (2002), pp. 148–160

    Google Scholar 

Download references

Author information

Authors and Affiliations

Authors

Corresponding author

Correspondence to Garrett S. Rose .

Editor information

Editors and Affiliations

Rights and permissions

Reprints and permissions

Copyright information

© 2014 Springer Science+Business Media New York

About this chapter

Cite this chapter

Rose, G.S., Kudithipudi, D., Khedkar, G., McDonald, N., Wysocki, B., Yan, LK. (2014). Nanoelectronics and Hardware Security. In: Pino, R. (eds) Network Science and Cybersecurity. Advances in Information Security, vol 55. Springer, New York, NY. https://doi.org/10.1007/978-1-4614-7597-2_7

Download citation

  • DOI: https://doi.org/10.1007/978-1-4614-7597-2_7

  • Published:

  • Publisher Name: Springer, New York, NY

  • Print ISBN: 978-1-4614-7596-5

  • Online ISBN: 978-1-4614-7597-2

  • eBook Packages: Computer ScienceComputer Science (R0)

Publish with us

Policies and ethics