Abstract
Digital Signal Processors have been developed for ages due to the great effectiveness in digital signal processing algorithms such as digital filtering and Fourier analysis which cannot be achieved in general-purpose processors. This work is to propose a VLIW architecture for Digital Signal Processor core including the top-level design of the data path. RTL implementation of the proposed architecture will be carried out in the future to verify the micro-architecture as well as instruction set of the DSP core.
This is a preview of subscription content, log in via an institution to check access.
Access this chapter
Tax calculation will be finalised at checkout
Purchases are for personal use only
Preview
Unable to display preview. Download preview PDF.
References
Nguyen, X.-T., Do, Q.-D., Tran, H.-D., Huynh, H.-T., Pham, C.-K.: A PCIe-based FFT Implementation for High-speed Spectrum Analysis. In: Proc. 3rd IEICE Int. Conf. Integrated Circuits and Devices in Vietnam, Danang, Vietnam, August 13-15, pp. 126–131 (2011)
Yagi, M., Shibata, T.: An Image Representation Algorithm Compatible with Neural-Associative-Processor-Based Hardware Recognition Systems. IEEE Trans. Neural Networks 14(5), 1144–1161 (2003)
Titlebaum, E.L.: Frequency- and time-hop coded signals for use in radar and sonar systems and multiple access communications systems. In: Conference Record of The Twenty-Seventh Asilomar Conference on Signals, Systems and Computers. Dept. of Electr. Eng., Rochester Univ., NY (1993)
Olswang, B.S.: Separation of Audio Signals Into Direct and Diffuse Soundfields for Surround Sound. In: Cvetkovic, Z. (ed.) Procs. of IEEE International Conference on Acoustics, Speech and Signal Processing. LOUD Technol. Inc., Wodinville (2006)
Mottl, V.: Pattern recognition in spatial data: a new method of seismic explorations for oil and gas in crystalline basement rocks. In: Dvoenko, S., Levyant, V., Muchnik, I. (eds.) Procs. of 15th Internation Conference on Pattern Recognition. Tula State Univ., Russia (2000)
Tan, E.J., Heinzelman, W.B.: DSP architectures: past, present and futures. SIGARCH Comput. Archit. News 31(3), 6–19 (2003)
Author information
Authors and Affiliations
Corresponding author
Editor information
Editors and Affiliations
Rights and permissions
Copyright information
© 2014 Springer-Verlag Berlin Heidelberg
About this paper
Cite this paper
Le-Huu, KN., Vu, T.T., Ho, D.N., Dinh-Duc, AV. (2014). Towards a VLIW Architecture for the 32-Bit Digital Signal Processor Core. In: Jeong, H., S. Obaidat, M., Yen, N., Park, J. (eds) Advances in Computer Science and its Applications. Lecture Notes in Electrical Engineering, vol 279. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-41674-3_109
Download citation
DOI: https://doi.org/10.1007/978-3-642-41674-3_109
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-642-41673-6
Online ISBN: 978-3-642-41674-3
eBook Packages: EngineeringEngineering (R0)