Abstract
Tri-Gate (TG) FinFETs are the most reliable option to get into deeply scaled gate lengths. This paper analyses an optimized 5 nm gate length (LG) n-channel TG Junctionless SOI FinFET by different spacer engineering techniques with hafnium based (HfxTi1-xO2) high-k dielectric in the gate stack. The device process parameters like dielectric spacer impact, nano-fin geometry variation, and power analysis along with DC, Analog/RF, and linearity metrics at the nanoscale are investigated. To increase the accuracy of results at lower gate lengths, quantum models are involved by using TCAD simulator. The proposed device shows excellent electrical characteristics with DIBL = 10.6 mV/V, SS = 63.6 mV/dec, switching ratio (ION/IOFF) = ~107 and good ON-OFF performance metric Q = gm/SS = 2.06 × 10−5 S-dec/μm-mV even at 5 nm LG. The performance impact of outer low-k spacer dielectric variation in dual-k spacer reveals that performance enhancement of ~77% in terms of switching ratio, reduction of leakage current by ~73%, and improvement of gm by ~10% have been noticed from SiO2 + HfO2 to Si3N4 + HfO2. However, due to high-k dielectric in dual-k spacer gate capacitances increases, which leads to deterioration of RF parameters like ft, τ, and GBW. The Air single-k spacer shows good performance for RF applications with ft = 600 GHz, τ = 1 ps, GBW = 1.23 THz and dynamic power = 0.095 fJ/μm at LG = 5 nm. However, the linearity characteristics deteriorates for dual-k spacers and higher dielectric single-k spacers (SiO2, Si3N4) has been noticed. This investigation reveals that at nanoscale Air spacer outperforms all other spacer combinations for low power applications and better linearity (low distortion), and assures further scaling for RF applications.
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References
Sahay S, Kumar MJ (2019) Junctionless field-effect transistors: design, modeling, and simulation. Wiley, Hoboken
Moore GE (2006) Lithography and the future of Moore's law. IEEE Solid-State Circuits Society Newsletter 11(3):37–42
Narendar V, Tripathi S, Naik RBS (2018) A two-dimensional (2D) analytical modeling and improved Short Channel performance of Graded-Channel gate-stack (GCGS) dual-material double-gate (DMDG) MOSFET. Silicon 10(6):2399–2407
Nowak EJ, Aller I, Ludwig T, Keunwoo Kim, Joshi RV, Ching-te Chuang, Bernstein K, Puri R (2004) Turning silicon on its edge double gate CMOS/FinFET technology. IEEE Circ Devices Mag 20(1):20–31
Sachid AB, Chen M, Hu C (2017) Bulk FinFET with low-k spacers for continued scaling. IEEE Trans Electron Devices 64(4):1861–1864
Colinge JP, Lee CW, Afzalian A, Akhavan ND, Yan R, Ferain I, Razavi P, O'Neill B, Blake A, White M, Kelleher AM, McCarthy B, Murphy R (2010) Nanowire transistors without junctions. Nat Nanotechnol 5(3):225–229
Colinge JP et al (2011) Junctionless transistors: physics and properties, semiconductor-on-insulator materials for Nanoelectronics applications, engineering materials. Springer-Verlag, New York, pp 187–200
Singh N, Agarwal A, Bera LK, Liow TY, Yang R, Rustagi SC, Tung CH, Kumar R, Lo GQ, Balasubramanian N, Kwong DL (2006) High-performance fully depleted silicon nanowire (diameter /spl les/ 5 nm) gate-all-around CMOS devices. IEEE Electron Device Lett 27(5):383–386
Biswas K, Sarkar A, Sarkar CK (2017) Spacer engineering for performance enhancement of junctionless accumulation-mode bulk FinFETs. IET Circ Devices Syst 11(1):80–88
Lee C et al (2010) High-temperature performance of silicon junctionless MOSFETs. IEEE Trans Electron Devices 57(3):620–625
Veeraraghavan S, Fossum JG (1989) Short-channel effects in SOI MOSFETs. IEEE Trans Electron Devices 36(3):522–528
Narendar V et al (2019) Investigation of short channel effects (SCEs) and analog/RF figure of merits (FOMs) of dual-material bottom-spacer ground-plane (DMBSGP) FinFET. Silicon 12:2283–2291
Subramanian V, Parvais B, Borremans J, Mercha A, Linten D, Wambacq P, Loo J, Dehan M, Gustin C, Collaert N, Kubicek S, Lander R, Hooker J, Cubaynes F, Donnay S, Jurczak M, Groeseneken G, Sansen W, Decoutere S (2006) Planar bulk MOSFETs versus FinFETs: an analog/RF perspective. IEEE Trans Electron Devices 53(12):3071–3079
Pal PK, Kaushik BK, Dasgupta S (2014) Investigation of symmetric dual-k spacer trigate FinFETs from delay perspective. IEEE Trans Electron Devices 61(11):3579–3585
Colinge J-P (2008) FinFETs and other multi-gate transistors. Springer-Verlag, New York
Narendar et al (2020) A novel bottom-spacer ground-plane (BSGP) FinFET for improved logic and analog/RF performance. AEU Int J Electron Commun 127:153459
Ko H, Kim J, Kang M, Shin H (2017) Investigation and analysis of dual-K spacer with different materials and spacer lengths for nanowire FET performance. Solid State Electron 136:68–74
Srivastava, N. A and Mishra, R. A. (2019) Linearity distortion assessment and small-signal behavior of Nano-scaled SOI MOSFET for terahertz application. ECS J Solid State Sci Technol 8: N234
Baidya, A., Lenka, T.R and Baishya, S (2020) Linear distortion analysis of 3D double gate Junctionless transistor with high-K dielectrics and gate metals. Silicon
Barraud S, Berthome M, Coquand R, Casse M, Ernst T, Samson MP, Perreau P, Bourdelle KK, Faynot O, Poiroux T (2012) Scaling of trigate junctionless nanowire MOSFET with gate length down to 13 nm. IEEE Electron Device Lett 33(9):1225–1227
Kumar R, Kumar A (2020) Hetro-dielectric (HD) oxide-engineered Junctionless double gate all around (DGAA) nanotube field effect transistor (FET). Silicon
Yu E, Heo K, Cho S (2018) Characterization and optimization of inverted-T FinFET under nanoscale dimensions. IEEE Trans Electron Devices 65(8):3521–3527
(2013). International Technology Roadmap for Semiconductors (ITRS). [Online]. Available: http://www.itrs2.net
(2008) Genius, 3-D Device Simulator, Version1.9.0, Reference Manual, Cogenda, Singapore
Lin J (1997) Fet device with double spacer. U.S. Patent 5 663 586, Sep. 2
Chen S et al (2015) ESD characterization of gate-all-around (GAA) Si nanowire devices, 2015 IEEE International Electron Devices Meeting (IEDM), Washington, DC 14.4.1–14.4.4, https://doi.org/10.1109/IEDM.2015.7409696
Pal PK, Kaushik BK, Dasgupta S (2015) Asymmetric dual-spacer Trigate FinFET device-circuit Codesign and its variability analysis. IEEE Trans Electron Devices 62(4):1105–1112
Thirunavukkarasu V, Jhan Y, Liu Y, Wu Y (2015) Performance of inversion, accumulation, and junctionless mode n-type and p-type bulk silicon FinFETs with 3-nm gate length. IEEE Electron Device Lett 36(7):645–647
Narendar V (2018) Performance enhancement of FinFET devices with gate-stack (GS) high-K dielectrics for Nanoscale applications. Silicon 10:2419–2429
Bousari NB, Anvarifard MK, Haji-Nasiri S (2019) Benefitting from high-κ spacer engineering in balistic triple-gate junctionless FinFET- a full quantum study. Silicon 12:2221–2228
Vadhitya N, Mishra RA (2015) Analytical modeling and simulation of multigate FinFET devices and the impact of high-k dielectrics on short channel effects (SCEs). Superlattice Microst 85:357–369
Gupta S, Nandi A (2017) Effect of air spacer on analog performance of underlap trigate FinFET. Superlattice Microst 109:693–701
Manikandan S, Balamurugan NB (2020) The improved RF/stability and linearity performance of the ultrathin-body Gaussian-doped junctionless FinFET. J Comput Electron 19:613–621
Sachid AB, Huang YM, Chen YJ, Chen CC, Lu DD, Chen MC, Hu C (2017) FinFET with encased air-gap spacers for high-performance and low-energy circuits. IEEE Electron Device Lett 38(1):16–19
Nandi A, Saxena AK, Dasgupta S (2013) Design and analysis of analog performance of dual-k spacer Underlap N/P-FinFET at 12 nm gate length. IEEE Trans Electron Devices 60(5):1529–1535
Narasimhulu T, Lakshmi B (2017) RF performance enhancement in multi-fin TFETs by scaling inter fin separation. Mater Sci Semicond Process 71:304–309
Chowdhury N, Iannaccone G, Fiori G, Antoniadis DA, Palacios T (2017) GaN nanowire n-MOSFET with 5 nm channel length for applications in digital electronics. Electron Dev Lett 38(7):859–862
Ryu D et al (2020) Design and optimization of triple-k spacer structure in two-stack Nanosheet FET from OFF-state leakage perspective. IEEE Trans Electron Devices 3(67):1317–1322
Saha R, Goswami R, Bhowmick B, Baishya S (2020) Dependence of RF/Analog and linearity figure of merits on temperature in ferroelectric FinFET: a simulation study. IEEE Trans Ultrason Ferroelectr Freq Control 11(67):2433–2439
Kumar A, Gupta N, Tripathi SK, Tripathi MM, Chaujar R (2020) Performance evaluation of linearity and intermodulation distortion of nanoscale GaN-SOI FinFET for RFIC design. AEU Int J Electron Commun 115:153052
Saha R, Bhowmick B, Baishya S (2020) Impact of lateral straggle on linearity performance in gate-modulated (GM) TFET. Appl Phys A Mater Sci Process 126:201
Acknowledgements
The authors thank to the department of Electronics and Communications Engineering, NIT Warangal for providing the TCAD Tools.
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V. Bharath Sreenivasulu: Writing- Original draft preparation, Formal Analysis, Investigation, Simulation, Data Curation.
V. Narendar: Conceptualization, Methodology, Supervision.
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Sreenivasulu, V.B., Narendar, V. A Comprehensive Analysis of Junctionless Tri-Gate (TG) FinFET Towards Low-Power and High-Frequency Applications at 5-nm Gate Length. Silicon 14, 2009–2021 (2022). https://doi.org/10.1007/s12633-021-00987-8
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DOI: https://doi.org/10.1007/s12633-021-00987-8