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Fabrication and characterization of metal-ferroelectric-insulator-Si diodes and transistors with different HfSiON buffer layer thickness

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Abstract

Metal-ferroelectric-insulator-Si (MFIS) structures using HfSiON as buffer layers were fabricated, and the impact of buffer layer thickness on the electrical properties of the MFIS devices was investigated. HfSiON films with thickness ranging from 1 to 4 nm were deposited by electron beam evaporation, which exhibited much reduced leakage current when compared to that of SiO2 with the same equivalent oxide thickness. From the viewpoint of polarization and charge injection, the flatband voltage and memory window width dependent on the sweeping voltages were discussed for the MFIS diodes with 1-, 2-, and 4-nm-thick HfSiON buffer layers. Small leakage current as well as excellent long-term data retention characteristics were found for all of these samples. It was also found that MFIS diodes with 2-nm-thick HfSiON buffer layer have the largest memory window width. Ferroelectric-gate transistors fabricated with a Pt/SBT(300nm)/HfSiON (2 nm)/Si gate structure showed a memory window of 0.8 V and a high drain current on/off ratio of 108 for the gate voltage sweep between +4 and −4 V. All of these excellent electrical properties proved that HfSiON acts as an excellent barrier for suppressing both leakage current and atomic interdiffusion.

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References

  1. H. Ishiwara: Recent progress in ferroelectric-gate FETs in Ferroelectric Thin Films XI, edited by D.Y. Kaufman, S. Hoffmann-Eifert, S.R. Gilbert, A. Aggarwal, and M. Shimizu, (Mater. Res. Soc. Symp. Proc.748, Warrendale, PA, 2003), U9.5

    Google Scholar 

  2. K-H. Kim, J-P. Han, S-W. Jung, T-P. Ma: Ferroelectric DRAM (FEDRAM) FET with Metal/SrBi2Ta2O9/SiN/Si gate structure. IEEE Electron Device Lett. 23, 82 2002

    Article  CAS  Google Scholar 

  3. J.P. Han, S.M. Koo, C.A. Ritchter, E.M. Vogel: Influence of buffer layer thickness on memory effects of SrBi2Ta2O9/SiN/Si structures. Appl. Phys. Lett. 85, 1439 2004

    Article  CAS  Google Scholar 

  4. H.S. Choi, E.H. Kim, I-H. Choi, Y.T. Kim, J.H. Choi, J.Y. Lee: The effect of ZrO2 buffer layer on electrical properties in Pt/SrBi2Ta2O9/ZrO2/Si ferroelectric gate oxide structure. Thin Solid Films 388, 266 2001

    Article  Google Scholar 

  5. B.E. Park, H. Ishiwara: Electrical properties of LaAlO3/Si and Sr0.8Bi2.2Ta2O9/LaAlO3/Si structures. Appl. Phys. Lett. 79, 806 2001

    Article  CAS  Google Scholar 

  6. A.D. Li, Y.J. Wang, Q.Y. Shao, J.B. Cheng, D. Wu, H.Q. Ling, Y.J. Bao, M. Wang, Z.G. Liu, N.B. Ming: Characteristics of SrBi2Ta2O9 ferroelectric films on Si using LaAlO3 thin film as an insulator. Appl. Phys. A 81, 1273 2005

    Article  CAS  Google Scholar 

  7. M. Takahashi, S. Sakai: Self-aligned-gate metal/ferroelectric/insulator/semiconductor field-effect transistors with long memory retention. J. Jpn. Appl. Phys. 44, L800 2005

    Article  CAS  Google Scholar 

  8. S. Sakai, R. Ilangovan: Metal-ferroelectric-insulator-semiconductor memory FET with long retention and high endurance. IEEE Electron Device Lett. 25, 369 2004

    Article  CAS  Google Scholar 

  9. K. Takahashi, K. Aizawa, B.E. Park, H. Ishiwara: Thirty-day-long data retention in ferroelectric-gate field-effect transistors with HfO2 buffer layers. J. Jpn. Appl. Phys 44, 6218 2005

    Article  CAS  Google Scholar 

  10. B.E. Park, K. Takahashi, H. Ishiwara: Five-day-long ferroelectric memory effect in Pt/(Bi,La)4Ti3O12/HfO2/Si structures. Appl. Phys. Lett. 85, 4448 2004

    Article  CAS  Google Scholar 

  11. X.B. Lu, K. Maruyama, H. Ishiwara: Metal-ferroelectric-insulator-Si devices using HfTaO buffer layers. Semicond. Sci. Technol. 23, 045002 2008

    Article  Google Scholar 

  12. X.B. Lu, K. Maruyama, H. Ishiwara: Characterization of HfTaO films for gate oxide and metal-ferroelectric-insulator-silicon device applications. J. Appl. Phys. 103, 044105 2008

    Article  Google Scholar 

  13. E.P. Gusev, V. Narayanan, M.M. Frank: Advanced high-kappa dielectric stacks with polySi and metal gates: Recent progress and current challenges. IBM J. Res. & Dev. 50, 387 2006

    Article  CAS  Google Scholar 

  14. H. Hoko, C. Aoki, Y. Tabuchi, T. Tamura, K. Maruyama, Y. Arimoto, H. Ishiwara: Electrical properties of Pt/BLT/HfSiON/Si structure for 1T-type ferroelectric memory. Integr. Ferroelectr. 79, 205 2006

    Article  Google Scholar 

  15. X. Wang, J. Liu, F. Zhu, N. Yamada, D-L. Kwong: A simple approach to fabrication of high-quality HfSiON gate dielectrics with improved nMOSFET performances. IEEE Trans. Electron. Devices 51, 1798 2004

    Article  CAS  Google Scholar 

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ACKNOWLEDGMENT

This work was performed under the auspices of the Special Coordination Funds for Promotion Science and Technology supported by the Ministry of Education, Culture, Sports, Science and Technology.

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Correspondence to Xubing Lu.

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Lu, X., Ishiwara, H. & Maruyama, K. Fabrication and characterization of metal-ferroelectric-insulator-Si diodes and transistors with different HfSiON buffer layer thickness. Journal of Materials Research 23, 2727–2732 (2008). https://doi.org/10.1557/JMR.2008.0336

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  • DOI: https://doi.org/10.1557/JMR.2008.0336

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