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Experimental Study of Etched Back Thermal Oxide for Optimization of the Si/High-k Interface

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Abstract

We have demonstrated a uniform, robust interface for high-k deposition with significant improvements in device electrical performance compared to conventional surface preparation techniques. The interface was a thin thermal oxide that was grown and then etched back in a controlled manner to the desired thickness. Utilizing this approach, an equivalent oxide thickness (EOT) as low as 0.87 nm has been demonstrated on high-k gate stacks having improved electrical characteristics as compared to more conventionally prepared starting surfaces.

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Acknowledgments

The authors thank the people in the International SEMATECH Advanced Tool Development Facility with the help in processing of wafers.

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Authors and Affiliations

  1. International SEMATECH, Austin, TX, USA

    Joel Barnett, N. Moumen, J. Gutt, M. Gardner, C. Huffman, P. Majhi, J.J. Peterson, S. Gopalan, B. Foran, H.-J. Li, B.H. Lee, G. Bersuker, P. M. Zeitzoff, G.A. Brown, P. Lysaght, C. Young, R.W. Murto & H.R. Huff

  2. IBM Assignee, USA

    N. Moumen & B.H. Lee

  3. AMD assignee, USA

    M. Gardner

  4. Texas Instruments assignee, USA

    C. Huffman & R.W. Murto

  5. Philips assignee, USA

    P. Majhi

  6. Infineon assignee, USA

    H.-J. Li

Authors
  1. Joel Barnett
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  2. N. Moumen
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  3. J. Gutt
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  4. M. Gardner
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  5. C. Huffman
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  6. P. Majhi
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  7. J.J. Peterson
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  8. S. Gopalan
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  9. B. Foran
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  10. H.-J. Li
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  11. B.H. Lee
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  12. G. Bersuker
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  13. P. M. Zeitzoff
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  14. G.A. Brown
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  15. P. Lysaght
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  16. C. Young
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  17. R.W. Murto
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  18. H.R. Huff
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Barnett, J., Moumen, N., Gutt, J. et al. Experimental Study of Etched Back Thermal Oxide for Optimization of the Si/High-k Interface. MRS Online Proceedings Library 811, 61–66 (2003). https://doi.org/10.1557/PROC-811-E1.4

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  • DOI: https://doi.org/10.1557/PROC-811-E1.4

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