Abstract
The need for greater reliability in the fault coverage of test sequences for VLSI circuits has led to the proposal for more accurate fault models and test pattern generation tools. Such improvements bring about a large increase in the fault list to be considered and in the CPU time needed to generate the test. In this article, we propose a global modeling allowing the definition of fault equivalence criteria in order to reduce the set of faults to be handled by the test pattern generation process for CMOS circuits. The proposed approach is based on a switch level description of the circuit. To perform fault equivalence on such descriptions, circuit modifications are introduced using subnetwork partitioning. The fault models taken into account are classical in CMOS technology, i.e., stuck-at, stuck-on, stuck-open, shorts and opens.
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This research is supported by the European Economic Community under regulation ESPRIT 2318 (EVEREST Project)
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Flottes, M.L., Landrault, C. & Pravossoudovitch, S. Fault modeling and fault equivalence in CMOS technology. J Electron Test 2, 229–241 (1991). https://doi.org/10.1007/BF00135440
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DOI: https://doi.org/10.1007/BF00135440