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Recent VLSI neural networks in Japan

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Abstract

In this article, recent research activities on the development of electronic neural networks in Japan are reviewed. Most of the largest Japanese electronic companies have developed VLSI neural chips using analog, digital or optoelectronic circuits. They have run various neural networks on them. Recently, in Japan, digital approach becomes active. Several fully-digital VLSI chips for on-chip BP learning have been developed, and 2.3 GCUPS (Giga Connection Updates per Second) learning speed has already been attained. Although the numbers of neurons and synapses containable in single digital chips are small, a large neural network can be developed by cascading the chips. By cascading 72 chips, a fully interconnected PDM (Pulse Density Modulating) digital neural network system has been developed. The behavior of the system follows simultaneous nonlinear differential equations and the processing speed amounts to 12 GCPS (Giga Connections per Second).

Intensive researches on analog and optoelectronic approaches have also been carried out in Japan. An analog VLSI neural chip attains 28 GCUPS on-chip learning speed and 1 TCPS (Tera Connections per Second) processing speed for Boltzmann machine with 1 bit digital output. For the optoelectronic approach, although the network size is small, 640 MCUPS BP learning speed has been attained.

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References

  1. M.A. Sivilotti, M.R. Emerling, and C.A. Mead, “VLSI architecture for implementation of neural networks,”Proceedings of the AIP Conference on Neural Networks for Computing, 1986, pp. 408–413.

  2. C.A. Mead and M.A. Mahowald, “A silicon model of early visual processing,”Neural Networks, vol. 1, 1988, pp. 91–97.

    Article  Google Scholar 

  3. H.P. Graf et al., “VLSI implementation of a neural network memory with several hundreds of neurons, ”Neural Networks for Computing, AIP, 1986.

  4. H.P. Graf and D. Henderson, “A reconfigurable CMOS neural network,”Proceedings of IEEE ISSCC'90, TPM 9.2, 1990, pp. 144–145.

    Google Scholar 

  5. Y. Arima, K. Mashiko, K. Okada, and T. Yamada, “A 336-neuron 28k-synapse self-learning neural network chip with branchneuron-unit architecture,”Proceedings of IEEE ISSCC'90, TPM 11.2, 1991, pp. 182–184.

  6. M. Yasunaga et al., “A self-learning neural network composed of 1152 digital neurons in wafer-scale LSIs,”Proceedings of IJCNN'91, vol. III, 1991, pp. 1845–1849.

  7. H. Eguchi et al., “Neural network LSI chip with on-chip learning,”Proceedings of IJCNN'91, 1991.

  8. B. Furman and A.A. Abidi, “An analog CMOS backward errorpropagation LSI,”Proceedings of First Annual INNS Symposium, 1988.

  9. M. Holler, S. Tarn, H. Casstro, and R. Benson, “An electrically trainable artificial neural network (ETANN) with 10240 floating gate synapses,”Proceedings of IJCNN'89, vol. II, 1989, pp. 191–196.

  10. T. Morishita, Y. Tamura, and T. Otsuki, “A BiCMOS analog neural network with dynamically updated weights,”Proceedings of IEEE ISSCC'90, TPM 9.1, 1990, pp. 142–143.

  11. A.J. Argranat, C.F. Neugebauer, and A. Yariv, “A CCD based neural network integrated circuit with 64K analog programmable synapses,”Proceedings of IJCNN'90, vol. II, 1990, pp. 551–555.

  12. H. Kato, Y. Sugiura, and S. Tsuchiya, “On implementing neurocomputer systems using analog neuroprocessor chips,”Technical Report of Information Processing Society of Japan, 89-ARC-78-2, 1989. (in Japanese)

  13. B.E. Boser and E. Säckinger, “An analog neural network processor with programmable network topology,”Proceedings of IEEE ISSCC91, TPM 11.3, 1991, pp. 184–185.

  14. P. Mueller et al., “Design and performance of a prototype analog neural computer,”Proceedings of the 2nd International Conference on Microelectronics for Neural Networks, 1991, pp. 347–357.

  15. A.F. Murray, D. Del Corso, and L. Tarassenko, “Pulse-stream VLSI neural networks mixing analog and digital techniques,”IEEE Transactions on Neural Networks, vol. 2, 1991, pp. 193–204.

    Article  Google Scholar 

  16. R.C. Frye, E.A. Reitman, C.C. Wong, and B.L. Chin, “An investigation of adaptive learning implemented in an optically controlled neural networks,”Proceedings of IJCNN'89, vol. II, 1989, pp. 457–463.

  17. K. Kyuma et al., “The first demonstration of an optical learning chip,”Optical Computing, 1991, pp. 291–294.

  18. M. Yasunaga et al., “A wafer scale integration neural network utilizing completely digital circuits,”Proceedings of IJCNN'89, vol. II, 1989, pp. 213–217.

  19. H. Kato, H. Yoshizasa, H. Ichiki, and K. Asakawa, “A parallel neurocomputer architecture towards Billion connection updates per second,”Proceedings of IJCNN'90, vol. II, 1990, pp. 47–50.

  20. Y. Shimokawa, Y. Fuwa, and N. Aramaki, “A parallel ASIC VLSI neurocomputer for a large number of neurons and billion connections per second speed,”Proceedings of IJCNN'91, vol. HI, 1991, pp. 2162–2167.

  21. U. Ramacher and J. Beichter, “Architecture of a systolic neuroemulator,”Proceedings of IJCNN'91, vol. II, 1991, pp. 2162–2167.

  22. A.F. Murray and A.V.W. Smith, “ Asynchronous VLSI neural networks using pulse-stream arithmetics,”IEEE Journal of Solid-State Circuits, vol. 23, 1988, pp. 688–697.

    Article  Google Scholar 

  23. J. Tomberg, T. Ritoniemi, K. Kaski, and H. Tenhuenen, “Fully digital neural network implementation based on pulse density modulation,”Proceedings of IEEE 1989 C1CC, 1989, pp. 12.7.1–12.7.4.

  24. Y. Hirai, K. Kamada, M. Yamada, and M. Ooyama, “A digital neuro-chip with unlimited connectability for large scale neural networks,”Proceedings of IJCNN'89, vol. II, 1989, pp. 163–169.

  25. Max Stanford Tomlinson, Jr., D.J. Walker, and M.A. Sivilotti, “A digital neural network architecture for VLSI,”Proceedings of IJCNN'90, vol. II, 1990, pp. 545–550.

  26. J.R. Beerhold, M. Jansen, and R. Eckmiller, “Pulse-processing neural net hardware with selectable topology and adaptive weights and delays,”Proceedings of IJCNN'90, vol. II, 1990, pp. 569–574.

  27. Y. Hirai,VLSI Neural Network Systems, Gordon and Breach Science Publishers, Reading, 1992.

    Google Scholar 

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Authors and Affiliations

  1. Institute of Information Sciences and Electronics, University of Tsukuba, 1-1-1 Ten-nodai, 305, Tsukuba, Ibaraki, Japan

    Yuzo Hirai

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  1. Yuzo Hirai
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Hirai, Y. Recent VLSI neural networks in Japan. J VLSI Sign Process Syst Sign Image Video Technol 6, 7–18 (1993). https://doi.org/10.1007/BF01581955

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