Skip to main content
Log in

La technologie asynchrone au service de la réduction d’énergie dans les systèmes embarqués

Asynchronous technology for energy reduction in embedded systems

  • Published:
Annales Des Télécommunications Aims and scope Submit manuscript

Résumé

Cet article présente les bénéfices en termes de réduction d’énergie des systèmes asynchrones comparativement aux systèmes synchrones dans le contexte des systèmes embarqués et notamment des équipements de télécommunications tels que les objets portables et communicants. La réduction de la consommation électrique est obtenue en agissant tant au niveau matériel qu’au niveau logiciel. Les techniques de mise en veille et d’adaptation dynamique de la tension d’alimentation pour les systèmes asynchrones sont étudiées et comparées aux systèmes synchrones. Enfin, une politique de gestion de l’énergie pour les microprocesseurs asynchrones est proposée dans le cadre de tâches périodiques et sporadiques.

Abstract

This article presents the benefits of asynchronous systems versus synchronous systems in term of energy reduction in the context of embedded systems and in particular for telecom equipments such as mobile communicating objects. The electrical consumption reduction is obtained at the hardware and software levels. The shutdown technique and the dynamic voltage scaling for asynchronous systems are studied and compared to synchronous systems. Finally, a power management policy is proposed for asynchronous microprocessors processing periodic and sporadic tasks.

This is a preview of subscription content, log in via an institution to check access.

Access this article

Price excludes VAT (USA)
Tax calculation will be finalised during checkout.

Instant access to the full article PDF.

Références

  1. Abrial (A.),Bouvier (J.),Renaudin (M.),Senn (P.) andVivet (P.), “A New Contactless Smart Card IC using On-Chip Antenna and Asynchronous Microcontroller”,ieee Journal of Solid-State Circuits,36 (2001) 1101–1107.

    Article  Google Scholar 

  2. Benini (L.),Bogliolo (A.),De Micheli (G.), “A Survey of Design Techniques for System-Level Dynamic Power Management”,ieee Transactions on Very Large Scale Integration (vlsi) Systems,8 (June 2000) 299–316.

    Article  Google Scholar 

  3. Burd (T.D.),Brodersen (R.W.), “Energy-Efficientcmos Microprocessor Design”,ieee Proc. 28th Hawaï Int. l’onf on System Sciences,1 (Jan 1995) 288–297.

    Google Scholar 

  4. Burd (T.D.),Pering (T.A.),Stratakos (A.J.),Brodersen (R.W.), “A dynamic voltage scaled microprocessor system”,ieee Journal of Solid-State Circuits,35 (Nov. 2000) 1571–1580.

    Article  Google Scholar 

  5. Chandrakasan (A.P.),Sheng (S.),Brodersen (R.W.), “Low Powercmos Digital Design”,ieee Journal of Solid-State Circuits,27 (April 1992) 473–484.

    Article  Google Scholar 

  6. Es Salhiene (M.),Fesquet (L.),Renaudin (M.), “Dynamic Voltage Scheduling for Real Time Asynchronous Systems”,Twelfth International Workshop onPower And Timing Modeling, Optimization and Simulation (patmos), Sevilla, Spain (11–13 September 2002).

  7. Flautner (K.), “Automatic Monitoring for Interactive Performance and Power Reduction”, Dissertation, Michigan University (2001).

  8. Fleischmann (M.), “Crusoe Longrun Power Management”, Transmeta Corporation, (17 January 2001).

  9. Govil (K.),Chan (E.),Wassermann (H.), “Comparing algorithms for dynamic speed-setting of a lowpowercpu”,acm International Conference on Mobile Computing and Networking, Berkeleyca usa (Nov. 1995) 13–25.

  10. Gowan (M.K.),Biro (L.L.),Jackson (D.B.), “Power Considerations in the Design of the Alpha 21264 Microprocessor”,ieee proc. 35th Design Automation Conference, San Francisco,ca usa (June 1998) 726–731.

  11. Kurnar (P.),Srivastava (M.), “Predictive Strategies for Low-Powerrtos Scheduling”,ieee Proc. Int. Conf On Computer design:vlsi in computers and processors, Austintx (Sept. 2000) 343–348.

  12. Li (Y.W.),Patounakis (G.),Jose (A.),Shepard (K.L.),Nowick (SM.), “Asynchronous datapath with software controlled on-chip adaptative voltage scaling for multirate signal processing application”,ieee Proc. Int. Symp. On Asynchronous Circuits and Systems, Vancouver,bc, Canada (May 2003) 216–225.

  13. Lu (Y.H.),Benini (L.),De Micheli (G.), “Operating-System Directed Power Reduction”, Proc.Int. Symposium on Low Power Electronic Design, Rapallo, Italy (July 2000) 37–42.

  14. Lu (Y.H.),De Micheli (G.), “Comparing System-Level Power Management Policies”,ieee Journal Design & test of Computers (2001) 10–19.

  15. Nielsen (L.S.),Niessen (C.),Sparso (J.),Van Berkel (J.), “Low Power Operation Using Self-Timed Circuits and Adaptative Scaling of the Supply Voltage”,ieee Transaction on Very large Scale Integration (vlsi) Systems,2 (December 1994) 391–397.

    Article  Google Scholar 

  16. Pedram (M.), “Design Technologies for Low Powervlsi”, Encyclopedia ofComputer Science and Technology,36. Inc. Marcel Dekker (1997) 73–96.

    Google Scholar 

  17. Pering (T.),Burd (T.),Broderesen (R.), “Dynamic Voltage Scaling and the Design of a Low-Power Microprocessor System”,Power-Driven Microarchitecture Workshop, in conjunction withInt. Symposium on Computer Architecture, Barcelona, Spain (June 1998).

  18. Pering (T.),Burd (T.),Brodersen (R.), “Voltage Scheduling in the 1parm Microprocessor System”, Proc.Int. Symposium on Low Power Electronic Design, Rapallo, Italy (July 2000) 96–101.

  19. Renaudin (M.), Vivet (P.), and Robin (F.), “aspro-216: A standard-cellqdi 16-bitrisc asynchronous microprocessor”, Proc.International Symposium on Advanced Research in Asynchronous Circuits and Systems, San Diego,ca, usa (1998) 22–31.

  20. Renaudin (M.),Vivet (P.),Robin (F.), “aspro: an Asynchronous 16-Bitrisc Microprocessor withdsp Capabilities”, Proc.esscirc 99, Duisburg, Germany (21–23 Sept. 1999) 28–31.

  21. Smit (G.J.M.),Havinga (P.J.M.), “A survey of energy saving techniques for mobile computers”,Moby Dick technical report (1997) http://www.cs.utwente.nlR-havinga/papers/energy.ps.

  22. Srivasta (M.B.),Chandrakasan (A.P.),Brodersen (R.W.), “Predictive System Shutdown and Other Architectural Techniques for Energy Efficient Programmable Computation”,ieee Transactions on very Large Scale Integration (vlsi) Systems,4, (March 1996) 42–55.

    Article  Google Scholar 

  23. Transmeta Corporation, “Crusoe Processor System Design Guide”, http://www.transmeta.com

  24. Site web du groupecis du laboratoiretima, http://tima.irnau.fr/cis

  25. Weiser (M.),Welch (B.),Demers (A.),Shenker (S.), “Scheduling for reducedcpu energy”, Proc.usenix Symposium on Operating Systems Design and Implementation, Monterey,ca, usa (Nov. 1994) 13–25.

Download references

Author information

Authors and Affiliations

Authors

Rights and permissions

Reprints and permissions

About this article

Cite this article

Fesquet, L., Es Salhiene, M. & Renaudin, M. La technologie asynchrone au service de la réduction d’énergie dans les systèmes embarqués. Ann. Télécommun. 59, 984–997 (2004). https://doi.org/10.1007/BF03180030

Download citation

  • Issue Date:

  • DOI: https://doi.org/10.1007/BF03180030

Mot clés

Key words

Navigation