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Area-Delay and Energy-Efficient Throughput-Scalable VLSI Architecture for SDR Channelizer

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Abstract

A software-defined radio (SDR) channelizer extracts narrowband channels from the wideband signal. The impulse response of this filter is required to change with the desired channel to be extracted from the wideband input. A reconfigurable filter is used instead of fixed filters to implement the channelizer in a resource-constrained environment. In this paper, we present a throughput-scalable reconfigurable architecture for SDR channelizer. The proposed structure processes a block of L input samples and produces one block of L outputs in every clock cycle. The register complexity of the proposed structure is independent of throughput, whereas multiplier and adder complexity increases proportionately. A significant number of registers are saved when the proposed structure is implemented for larger filter-length and higher block-sizes. Theoretical estimates show that the proposed structure for the block-size 8 and filter-length 32 involves 256 extra multipliers and 105 extra adders against 6912 MUXes, 8 less registers than those of the existing similar structure, and it offers 8 times higher throughput. ASIC synthesis result shows that the proposed structure of block-size 8 and filter-length 32 involves 41 % less area-delay product and 22 % less energy per sample than those of the existing structure and offers nearly 6 times higher sampling rate than the other. At the normalized sampling rate, the proposed structure for filter-length 16 consumes 18 % and 22 % less power than the existing structure for block-sizes 4 and 8, respectively.

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Authors and Affiliations

  1. Department of Electronics and Communication Engineering, Jaypee University of Engineering and Technology, AB-Road, Raghogarh, Guna, Madhya Pradesh, 473226, India

    Basant Kumar Mohanty & Subodh Kumar Singhal

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  1. Basant Kumar Mohanty
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  2. Subodh Kumar Singhal
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Correspondence to Subodh Kumar Singhal.

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Mohanty, B.K., Singhal, S.K. Area-Delay and Energy-Efficient Throughput-Scalable VLSI Architecture for SDR Channelizer. Circuits Syst Signal Process 35, 2958–2971 (2016). https://doi.org/10.1007/s00034-015-0183-5

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  • DOI: https://doi.org/10.1007/s00034-015-0183-5

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