1 Introduction

Advanced CMOS technologies are driven by requirements of digital circuits to lower area and power consumption while increasing speed. These requirements are achieved by reducing both the transistors’ size and the supply voltage. However, the transistors’ threshold voltage cannot be similarly reduced as this would lead to an increase in the leakage current. These trends represent a stringent restriction to analog design, as the dynamic range is strongly limited, especially in the design of amplifiers. Therefore, most recent advances in high sampling frequency analog-to-digital converters (ADCs) are in successive approximation register (SAR) and in flash topologies. Since they do not require amplifiers and use only comparators, they are more suitable to be implemented in advanced digital CMOS processes (Fig. 1).

Fig. 1
figure 1

ADC sample frequency of recent publications [12]

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Flash ADCs are used when low latency and high sampling frequency are essential requirements. An N-bit flash (full-parallel) ADC (Fig. 2) is composed of a resistor ladder, a bank of \(2^{N}-1\) comparators and an encoder to convert the “thermometer code” to a binary output. The comparators are required to have low input offset voltage \((V_\mathrm{OS})\) and are responsible for the high power consumption and large area of the ADC: a reduced \(V_\mathrm{OS}\) requires large transistors (ADC with large area and high input capacitance), leading to a lower analog bandwidth and/or high power consumption. In deep submicron technologies, this effect prevents the use of small transistors, thus undermining the potential increase in sampling frequency or the reduction in power consumption, made possible by the new technologies. Several ingenious techniques to mitigate the effects of the comparators’ deterministic offset voltage have been presented.

Fig. 2
figure 2

Block diagram of a conventional flash ADC

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To prevent large errors due to bubbles in the thermometer code [9, 15], the most effective procedure is to use a Wallace tree encoder [14, 18]. Concerning the analog sector, in addition to designing the comparators with larger transistors, recently proposed approaches use redundancy, i.e., more comparators than necessary, but smaller, having an increased \(V_\mathrm{OS}\). Redundancy techniques usually require a foreground calibration step or even post-manufacturing statistical selection [3, 4, 7, 10, 11, 16, 19]. A more disruptive approach is proposed in [2, 20]: the ADCs have no reference ladder and rely on having accurate knowledge on the stochastic distribution of the comparators offset voltage allowing to estimate the code. This technique avoids calibration, but requires prior knowledge of the statistical distribution of \(V_\mathrm{OS}\). In [8] the number of comparators is reduced by using multiplexing processes, using less comparators with larger transistors. However, all the results are obtained only by circuit simulation and no experimental results are presented. In [1] the digital encoder is improved by using custom digital gates with less transistors.

The ADCs proposed in this paper also rely on the stochastic distribution of \(V_\mathrm{OS}\), but the approach is different; each comparator has a different reference voltage; and calibration, trimming, or the exact knowledge of the \(V_\mathrm{OS}\) distribution are not required. The ADC circuit remains almost as simple as the original; it can be used with advanced nanoscale technologies and allows easy porting between technologies.

The conventional parallel ADC will be referred to, in this paper, simply as flash ADC. The modified ADCs proposed here have also a parallel architecture, but they are offset tolerant (OST). They will be referred to in this paper as OST ADCs.

This paper is organized in seven sections. In Sect. 2, the OST flash ADC is presented. In Sect. 3, the effect of stochastic offset voltage on the ADC parameters is determined. In Sect. 4, the number of extra comparators to ensure full-scale operation is estimated. In Sect. 5, the expected gains in die area and power relative to the conventional flash ADC are calculated. In Sect. 6, the design flow and extreme case of an 8-bit ADC with a target ENOB of 4.5 bits are presented, and characterized, to demonstrate the proposed approach. Finally, in Sect. 7, conclusions are summarized.

2 Proposed Offset Tolerant (OST) Flash ADC

Moderate values of \(V_\mathrm{OS}\) cause missing codes and a non-monotonic transfer characteristic, reducing the fabrication yield drastically. A Wallace tree encoder [14] instead of deciding on a transition “\(0\rightarrow 1\)” in the thermometer code (classical encoder) counts the number of “1’s,” and it has been used for moderate values of \(V_\mathrm{OS}\) to avoid non-monotonicity and missing codes. In the architecture proposed here, this is taken to the extreme of letting the comparators have the highest offset voltage by using transistors with minimum dimensions. The order of the comparators does not matter if the encoder counts the number of “1’s.” The result is equivalent to reordering the comparators with the transitions appearing in sequence so, for a large number of comparators, the reordered transitions will be close to a uniform distribution.

This is exemplified in Fig. 3, where the transfer characteristic of a 4-bit flash ADC is represented, using comparators with large offset voltages without (flash) or with reordering (OST). The above reasoning fails for the comparators with reference voltages near the extremes of the input voltage range, which may have their decision points out of the input range, due to large values of \(V_\mathrm{OS}\). To take into account this effect, a small number of additional comparators are added with reference voltages beyond the limits of the input range at both extremes.

Fig. 3
figure 3

Transfer characteristic of a 4-bit ADC with high \(V_{\mathrm{OS}}\) for a flash and b OST

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3 Effect of Stochastic Offset Voltage on ADC Parameters

The most important static parameters that characterize an ADC are differential and integral nonlinearity (DNL and INL). The most important dynamic parameter is the signal-to-noise and distortion ratio (SINAD), which can be used to calculate the effective number of bits (ENOB). To evaluate the effect of extremely high offset voltages on the transfer characteristic and on the expected ENOB, a high-level model of a flash ADC with comparators having independent offset voltages was implemented. The comparators input offset voltage, \(V_\mathrm{OS}\), is assumed to be a random variable with a Gaussian distribution with a zero mean value \(({\mu }=0)\) and a certain variance value \(({\sigma }^{2})\).

This assumption (Gaussian distribution for the comparator \(V_\mathrm{OS}\)) holds, even if the mismatch distribution in the individual transistors is not Gaussian and has nonzero mean (as happens in some advanced technologies in which they are closer to Poisson’s distributions). For fully differential comparators, \(V_\mathrm{OS}\) has zero mean because the circuit is fully symmetric and there are several sources of mismatch; therefore, by the central limit theorem, the offset voltage will have zero mean and be approximately normally distributed.

The simulation results show that if a high number of comparators is considered and their positions are reordered by using the OST method, the DNL and INL are strongly reduced, as can be seen in the example of Fig. 4, where 285 comparators, with a \({\sigma } (V_\mathrm{OS})\) of 5 LSB, produce a DNL of 21.3 LSB and an INL of 15.2 LSB in the flash ADC (left hand side of Fig. 4); these values are reduced to 4.3 LSB and 4.7 LSB in the OST ADC (right hand side of Fig. 4). As shown in Fig. 5, the DNL and INL increase slowly with increasing \({\sigma } (V_\mathrm{OS})\) and tend to a limit value if additional comparators are added at the extremes of the input range.

Fig. 4
figure 4

DNL and INL in a flash and b OST ADCs (2000 cases) for \({\sigma } (V_{\mathrm{OS}}) = 5~\hbox {LSB}\)

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Fig. 5
figure 5

8-Bit flash and OST ADCs (with or without extra comparators): a DNL and b INL errors

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The average values of ENOB as a function of normalized \({\sigma } (V_\mathrm{OS})\) for an 8-bit ADC are presented in Fig. 6, for flash and OST converters with 7 and with 15 extra comparators with reference voltages beyond both the extremes of the input range. For the OST circuit, after an initial sharp drop, ENOB tends to decrease slowly, even for large \({\sigma } (V_\mathrm{OS})\). This behavior can also be observed in 6- and 10-bit ADCs of flash and OST types without or with the extra comparators (3 and 31, for 6- and 10-bit ADCs). In the OST ADC, the loss of accuracy is practically the same for converters with 6, 8 and 10 bits. Figure 7 shows the yield, defined as the fraction of ADCs that exhibit \(\hbox {ENOB}>\,N-0.5\), calculated from 2000 samples for each value of \({\sigma } (V_\mathrm{OS})\) considered.

Fig. 6
figure 6

ENOB of flash ADC and OST ADC (with or without extra comparators)

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Fig. 7
figure 7

Yield of 6-, 8- and 10-bit ADCs, a losing 2.5 bits on a flash ADC and b losing 2.5 bits and c losing 3.5 bits on an OST ADC

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For the flash ADC, the yield is about 90 % for \({\sigma } (V_\mathrm{OS}) < 0.28V_{\mathrm{LSB}}\) (for all resolutions \(N = 6,\, 8\) and 10 bits). This requirement is very difficult to meet, since for practical cases \(V_{\mathrm{LSB}}\) is a few millivolts. Establishing the equivalent yield for an OST ADC with extra comparators, and accepting the loss of additional 2 bits (ENOB \(> N\)-2.5), we achieve the same yield for a higher \({\sigma } (V_\mathrm{OS}): {\sigma } (V_\mathrm{OS}) < 4.2V_{\mathrm{LSB}}\). Accepting a loss of additional 3 bits (ENOB \(> N\)-3.5), the offset voltage can sharply increase to \({\sigma } (V_\mathrm{OS}) < \,17V_{\mathrm{LSB}}\) (even higher for the 10-bit ADC), which relaxes strongly the comparators \({\sigma } (V_\mathrm{OS})\) specification.

4 Extra Comparators

Voltage comparator’s reference has a deterministic value obtained from the resistor ladder, plus a random component, which is the comparator’s input offset voltage \(V_\mathrm{OS}\).

In this section, we will refer to a comparator’s “position” as the value of its reference voltage with respect to the input range.

In the middle zone of the input range, the probability of a comparator moving away from its desired position is the same as another comparator moving into that position. In the extremes of the input range, there are no comparators beyond the extreme to “jump in” to compensate those that “jump out.” This problem can be overcome by adding extra comparators beyond the extremes of the input range, i.e., with reference voltages outside the input voltage range.

To estimate the number of extra comparators that are necessary, we make the assumption that \(V_\mathrm{OS}\) has a Gaussian distribution with zero mean and standard deviation \({\sigma } (V_\mathrm{OS})\). We further assume that the \(V_\mathrm{OS}\) of different comparators are not correlated. To achieve a uniform distribution inside the input range, it is considered that the expected value of the number of comparators that are active beyond an established limit \(N_{\mathrm{JUMP}}\) can be given by (1), where \(p_{i}\) is the probability of comparator in the position i to be active beyond the established limit, \(x_{i}\) is the binary variable that defines the comparator state (one if active, zero if not), and n is the number of comparators used.

$$\begin{aligned} E\left\{ {N_{\mathrm{jump}}} \right\} =\mathop \sum \limits _{i=1}^n p_i \,x_i \end{aligned}$$
(1)

The expected value of (1) with only the active comparators (\(x_{i} = 1\)) leads to (2), which is calculated using (3) and (4).

$$\begin{aligned} E\left\{ {N_{\mathrm{jump}} } \right\}= & {} \mathop \sum \limits _{i=1}^n P\left( {x>0} \right) \times 1 \end{aligned}$$
(2)
$$\begin{aligned} P\left( {x>0} \right)= & {} 1-P\left( {x\le 0} \right) \end{aligned}$$
(3)
$$\begin{aligned} P\left( {x\le 0} \right)= & {} \int _{-\infty }^x \phi \left( t \right) \,\mathrm{d}t \end{aligned}$$
(4)

The probability in (4) is evaluated using the CDF defined by (5), given the result present in (6), where \(\hat{x}\) is the normalized value of x in \(V_{LSB}\), and the standard deviation \(\hat{{\sigma }}\) is given in LSB units.

$$\begin{aligned} F\left( {x\,;{\mu } \, ,{\sigma }^{2}} \right)= & {} \frac{1}{\sqrt{2\pi }\,{\sigma } }\int _{-\infty }^0 \mathrm{e}^{-\left( {\frac{x-{\mu } }{\sqrt{2}\,{\sigma } }} \right) ^{2}}\mathrm{d}x \end{aligned}$$
(5)
$$\begin{aligned} E\left\{ {N_{\mathrm{jump}} } \right\}= & {} \mathop \sum \limits _{i=1}^n \left\{ {1-\frac{1}{\sqrt{2\pi }\,\hat{{\sigma }} }\int _{-\infty }^0 \mathrm{e}^{-\left[ {\frac{\hat{x} +\left( {i-0.5} \right) }{\sqrt{2}\,\hat{{\sigma }}}} \right] ^{2}}\mathrm{d}\hat{x}} \right\} \end{aligned}$$
(6)

Using \(\hbox {MATLAB}^{{\circledR }}\) to evaluate (6), we can estimate the expected value of the number of active comparators that jump out the input range, illustrated on the graphics of Fig. 8, where the standard deviation changes from 1 to 39.

Fig. 8
figure 8

Graph of expected value of the number of active comparators that jump out the input range versus existing comparators and table with the first 13 values of line W

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It is possible to conclude that for a given number of comparators, the expected number of comparators that jump out tends to a limit, because comparators that are further away from the extreme are very less likely to jump out. The dot marked on each line set the expected number of comparators that jump to outside (to <10 % of the maximum observed, the highest admissible error). Each of this value can be achieved if there is at least the number of comparators given by \(N_{\mathrm{needed}}\). It is possible to see an almost linear dependence between these quantities (black-line in Fig. 8), especially for high \({\sigma } \), translated by Eqs. (7) and (8), obtained using a simple linear regression method.

$$\begin{aligned} E\left\{ {N_{\mathrm{jump}} } \right\}\approx & {} 0.40\times {\sigma } \left( {V_\mathrm{OS} } \right) \left[ {\hbox {LSB}} \right] \end{aligned}$$
(7)
$$\begin{aligned} E\left\{ {N_{\mathrm{needed}} } \right\}\approx & {} 2.5\times {\sigma } \left( {V_\mathrm{OS} } \right) \left[ {\hbox {LSB}} \right] -5 \end{aligned}$$
(8)

For each increment of 2.5 LSB in the value of \({\sigma } (V_\mathrm{OS})\), another comparator jumps over the limit. For example, in a parallel 8-bit ADC with 255 reference levels, if the standard deviation is 7 LSB, it is estimated that three comparators may be active beyond the characteristic limits. It can also be estimated that at least 12 additional comparators are required beyond each limit, to obtain the same probability of having three comparators being active inside the input range, replacing the previous ones. These theoretical results were confirmed by high-level simulation with 1000 different cases for each value of \({\sigma } (V_\mathrm{OS})\) considered. We have found that a lower number than that established by this rule is usually sufficient to avoid significant degradation of the performance of the OST ADC. In the example below (Sect. 6), \({\sigma } (V_\mathrm{OS}) = 15~\hbox {LSB}\) and we use only 15 (instead of 32) extra comparators at each extreme.

5 Expected Gains in Area and Power

To evaluate the advantage of using an \((N+m)\)-bit OST ADC against a flash ADC with N-bit, we consider that \({\sigma } (V_\mathrm{OS})\) is inversely proportional to the square root of the comparator area (9) [13]. Using dynamic comparators, which have only dynamic power dissipation, this is proportional to the parasitic capacitances and, hence, to the area (10).

$$\begin{aligned} {\sigma } \left( {V_\mathrm{OS} } \right)\propto & {} 1/\sqrt{W\cdot L} \end{aligned}$$
(9)
$$\begin{aligned} \hbox {``Power'' }\propto & {} \,\hbox {``Area''}\, \propto \, W\cdot L \end{aligned}$$
(10)

Table 1 shows a comparison in area and power between a conventional 6-bit flash ADC and an 8-bit OST ADC with extra comparators. For the 6-bit ADC, it is assumed, for comparison purposes, the case where \({\sigma } (V_\mathrm{OS})=4~\hbox {mV}\). For the 8-bit ADC, four different cases are presented: \({\sigma } (V_\mathrm{OS})=8~\hbox {mV}, {\sigma } (V_\mathrm{OS})=16~\hbox {mV}, {\sigma } (V_\mathrm{OS})=32~\hbox {mV}\) and \({\sigma } (V_\mathrm{OS}) = 64~\hbox {mV}\). As it can be seen from Table 1, relaxing the \({\sigma } (V_\mathrm{OS})\) to 8 mV has no advantage, since the comparators can have 1/4 the area and 1/4 the power, but it requires four times more comparators, leading to no overall advantage. In fact with the overhead of a larger encoder and more routing, it will even be unfavorable.

Table 1 Flash 6-bit ADC versus an 8-bit OST ADC, with 1 V full scale
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However, if we further relax the \({\sigma } (V_\mathrm{OS})\) to 16 mV, the area and power of the comparators reduce by a factor 16, which compensates largely the fourfold increase in the number of comparators. In this case, the gains in area and power are improved by a factor of 4. Finally, for even larger \({\sigma } (V_\mathrm{OS})\) (cases 32 and 64 mV), the overall gain becomes even more noticeable. This saving in the analog sector area dominates the increase in the area of the digital sector due to the increased number of nominal bit (with modern technologies, digital circuits can have very low area). We can derive that this architecture can be advantageous for the case where we have extra small transistors leading to comparators with larger offsets but with very small area and power for the same speed of operation. Furthermore, the advantage of the OST method is a large saving in design effort of the comparator, as it leads to a smoother degradation of performance and a large increase in offset voltage is no longer a major concern; this simplifies the porting between technologies.

In [5] the model used in this section was shown to be simplistic, the \(V_\mathrm{OS}\) reduction with the increase in W and L being less effective. However, this reinforces the advantage of the OST ADC, since to reduce \(V_\mathrm{OS}\), even larger transistors would be required.

6 Example: 8-bit OST ADC with 4.5 ENOB

To demonstrate the OST converters proposed here, we have designed an 8-bit ADC targeting a 4.5-bit ENOB, in UMC 130 nm CMOS technology, with dynamic latched comparators [17] with minimum dimension transistors, \((W/L)_{\mathrm{n}}=160~\hbox {nm}/120~\hbox {nm}\) for the NMOS transistor and \((W/L)_{\mathrm{p}}=400~\hbox {nm}/120~\hbox {nm}\) to match the complementary PMOS transistor using a kickback noise reduction network [6]. The circuit implementation of the 8-bit ADC circuit comprises: the above-mentioned comparators; a reference generator, based on a resistor ladder; three Wallace tree encoders; and a scan network. The scan network allows the measurement of the offset voltage of all comparators individually, and it also allows the construction of the static transfer characteristic (STC) of the flash and OST ADCs to obtain the static parameters (INL and DNL). The ADC block diagram is shown in Fig. 9, the comparator circuit in Fig. 10, the Wallace tree encoder configuration in Fig. 11, and the full adder implementation in Fig. 12.

Fig. 9
figure 9

Block diagram of the OST ADC prototype

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Fig. 10
figure 10

Dynamic latched comparator with the kickback noise suppression network

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Fig. 11
figure 11

Block diagram of \((2^{N}-1)\) to N Wallace tree encoder

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Fig. 12
figure 12

Full adder implementation

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6.1 OST Design Flow

The OST ADC design flow is shown in Fig. 13. First, we define the wanted ENOB, in our case 4.5-bit, and we design the yield graph accordingly for several ADC resolutions and yield (Fig. 14). Simultaneously, we design the comparator, with transistors sized with \((W/L)_{\mathrm{n}}=160~\hbox {nm}/120~\hbox {nm}, (W/L)_{\mathrm{p}}=400~\hbox {nm}/120~\hbox {nm}\) for the NMOS and the PMOS, respectively, and estimate by Monte Carlo simulations the offset voltage, for a large number of comparators (3200 in our case) distributed for different reference voltages as shown in Fig. 15 and obtained the value of \({\sigma } (V_\mathrm{OS})= 58~\hbox {mV}\).

Fig. 13
figure 13

OST flash design flow

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Fig. 14
figure 14

Yield for the OST flash for 6, 7, 8 and 9 bits, having 4.5 bits of ENOB

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Fig. 15
figure 15

OST flash design flow

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To determine the ADC resolution, we use the \({\sigma } (V_\mathrm{OS})= 58~\hbox {mV}\approx 14.8V_{\mathrm{LSB}}\) and a wanted yield of 90 % in Fig. 14 and this leads to an ADC resolution of 8 bits.

To determine the number of extra comparators, we use Eq. (5) and obtain 32 comparators.

6.2 OST ADC Prototype

An OST ADC prototype is designed in UMC’s 130-nm process to validate and show the feasibility and the potential of the proposed OST architecture comprising extra blocks for additional characterization measurements. We have decided to use only 15 extra comparators on each side of the input dynamic range to observe also the saturation of the ADC transfer characteristic. Figure 16 shows the layout of the integrated circuit where the building blocks are highlighted. The area of the entire circuit is \(400~{\upmu }\hbox {m }\times 150~{\upmu }\hbox {m}\) and is not minimized, especially the digital block, that can be reduced significantly (around 50 %) by using abutment technique in the layout design and removing the scan network (not necessary in a normal ADC operation).

Fig. 16
figure 16

Layout of the OST ADC demonstrator with an area of \(400~{\upmu }\hbox {m} \times 150~{\upmu }\hbox {m}\)

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We have tested three samples of the ADC comprising a total of 855 comparators (die photograph in Fig. 17), the use of a scan network at the comparators output allowed to measure the stochastic component of the comparators offset voltage which is \({\sigma } (V_\mathrm{OS})=68~\hbox {mV} ({\approx }17V_{\mathrm{LSB}})\) (see Table 2) slightly higher than the simulation result. For this value, the theoretical values for maximum DNL and INL (Fig. 5), for a conventional flash ADC, are \(72.5~V_{\mathrm{LSB}}\) and \(51.8~V_{\mathrm{LSB}}\), respectively. The flash ADC exhibits a non-monotonic behavior and has many missing codes. For the proposed OST ADC with 15 extra comparators, the theoretical values for DNL and INL (Fig. 5) are improved to \(5.1~V_{\mathrm{LSB}}\) and \(8.2~V_{\mathrm{LSB}}\). The static transfer characteristic is always monotonic without missing codes; therefore, it is meaningful to calculate the ENOB and its estimated mean value is 4.6-bit.

Fig. 17
figure 17

Die photograph of the OST ADC demonstrator

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Table 2 DNL, INL and ENOB for the three samples of the test circuit
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As shown in Table 2, the experimental measurements, obtained after offset and gain correction, are very similar for the three samples and agree with the theoretical values. The DNL average of the three samples is 5.35 LSB, slightly higher than the theoretical estimate of 5.1 LSB. The INL average is 9.26 LSB, higher than the theoretical estimate of 8.2 LSB. The main reason for the INL deviation results from an observed fluctuation in the reference voltages due to the residual kickback noise of the comparators.

In Fig. 18a, the STC for Sample no. 3 is shown for the flash and the OST ADCs. The 3 STCs, shown in Fig. 18b (\(V_{ip}\) is the voltage at one of the terminals of differential input voltage), exhibit offset and gain errors due to a small asymmetry inserted in the layout of the comparators, resulting in a deterministic error present in all the three samples. Although this asymmetry was not introduced deliberately, it turned out to be useful to show the different effects of deterministic and stochastic offset. This confirms that the errors from stochastic origin are mitigated while the deterministic errors are not corrected, requiring a careful layout. As the demonstrator has only 15 extra comparators, less than the estimated number of 32 extra comparators [from (8)], a higher nonlinearity at the extremes of the STC is also observed, as expected. The obtained experimental ENOB is 0.6 lower than the MATLAB simulating result, due to the deterministic errors (not corrected), and the additional noise added by the test setup.

Fig. 18
figure 18

Static transfer characteristic of: a one sample test circuit (flash and OST); b the three samples of the OST circuit

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To get similar results (4.5-bit ENOB) with a conventional 6-bit flash ADC, it would be necessary to substantially increase the dimension of the comparator transistors, resulting in a much higher area and power consumption.

7 Conclusion

A new approach to the design of a flash ADC is proposed, which relaxes the comparator requirements, ensures a monotonic characteristic and leads to less area and lower power consumption when compared with a conventional flash ADC having an equivalent ENOB. We show that using small transistors in the comparators, resulting in an offset voltage standard deviation as high as 17 LSB, the proposed technique leads to an 8-bit OST ADC with an ENOB of 4.5-bit, while a conventional 6-bit topology for the same performance would require comparators employing much larger transistors increasing the ADC die area and power.

This approach can be applied directly with more advanced digital-based technologies used in VLSI systems and can be easily ported. The proposed ADC characteristics are obtained by high-level simulations and are confirmed by experimental results from a proof-of-concept circuit, designed in UMC’s 130-nm process, using comparators with minimum dimension transistors, i.e., \((W/L)_{\mathrm{n}}=160~\hbox {nm}/120~\hbox {nm},\, (W/L)_{\mathrm{p}}=400~\hbox {nm}/120~\hbox {nm}\) for the NMOS and the PMOS, respectively.