Abstract
In this paper, a low-power CMOS analog automatic action potential (AP) detector is proposed for wireless neural recording implants. The proposed AP detector is based on comparing the neural input signal with an analog threshold level. The threshold level is obtained by calculating the root mean square value of the neural input signal. In order to generate the threshold voltage level, the AP detector incorporates a continuous-time (CT) sigma-delta (Σ∆) modulator in its analog signal processing section. This structure benefits from the combination of a CT Σ∆ modulator and a single-bit DAC as the multiplier to reduce the power consumption. Although in contrast to the traditional methods, the required circuits are not biased in the subthreshold region, the total power consumption is reduced. The proposed AP detector is designed in TSMC 90 nm CMOS technology and consumes 11.8 µW from a single 1-V power supply. It is worth mentioning that the utilized CT Σ∆ modulator can also be used in the analog-to-digital converter to significantly reduce both the power consumption and silicon area of the complete neural recording system.
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References
M.A. Al-Absi, A. Hussein, M. TaherAbuelma’atti, A low voltage and low power current-mode analog computational circuit. Circuits Syst. Signal Process. 32(1), 321–331 (2013)
P. Amaral, J. Goes, N. Paulino, A. Steiger-Garção, An improved low-voltage low-power CMOS comparator to be used in high-speed pipeline ADCs. IEEE Int. Symp. Circuits Syst. 5, 141–144 (2002)
M. Barati, M. Yavari, A power conversion chain with an internally-set voltage reference and reusing the power receiver coil for wireless bio-implants. Microelectron. J. 74(4), 69–78 (2018)
S. Barati, A.M. Sodagar, Discrete-time automatic spike detection circuit for neural recording implants. Electron. Lett. 47(5), 306–307 (2011)
C. Chen, J. Fan, X. Hu, Y. Hei, A low power, high performance analog front-end circuit for 1 V digital hearing aid SoC. Circuits Syst. Signal Process. 34(5), 1391–1404 (2015)
M. Delgado-Restituto, A. Rodríguez-Pérez, A. Darie, C. Soto-Sánchez, E. Fernández-Jover, Á. Rodríguez-Vázquez, System-level design of a 64-channel low power neural spike recording sensor. IEEE Trans. Biomed. Circuits Syst. 11(2), 420–433 (2017)
Q.-H. Duong, Q. Le, C.-W. Kim, S.-G. Lee, A 95-dB linear low-power variable gain amplifier. IEEE Trans. Circuits Syst. I Regul. Pap. 53(8), 1648–1657 (2006)
G. Ferri, S. Pennisi, S. Sperandii, A low-voltage CMOS 1-Hz low-pass filter, in IEEE International Conference on Electronics, Circuits and Systems (ICECS) (1999), pp 1341–1343
B. Gosselin, M. Sawan, An ultra low-power CMOS automatic action potential detector. IEEE Trans. Neural Syst. Rehabil. Eng. 17(4), 346–353 (2009)
R.R. Harrison, P.T. Watkins, R.J. Kier, R.O. Lovejoy, D.J. Black, B. Greger, F. Solzbacher, A low-power integrated circuit for a wireless 100-electrode neural recording system. IEEE J. Solid State Circuits 42(1), 123–133 (2007)
Z. Hojati, M. Yavari, An NTF-Enhanced Incremental ΣΔ Modulator Using A SAR Quantizer. Integr. VLSI J. 55(9), 212–219 (2016)
M. Jalalifar, G.-S. Byun, An ultra-low power spike detector for implantable biomedical systems, in IEEE Wireless and Microwave Technology Conference (WAMICON)(2013), pp 1–4
E. Koutsos, S.E. Paraskevopoulou, T.G. Constandinou, A 1.5 μW NEO-based spike detector with adaptive-threshold for calibration-free multichannel neural interfaces, in IEEE International Symposium on Circuits and Systems (ISCAS) (2013), pp 1922–1925
M.H. Maghami, A.M. Sodagar, M. Sawan, Versatile stimulation back-end with programmable exponential current pulse shapes for a retinal visual prosthesis. IEEE Trans. Neural Syst. Rehabil. Eng. 24(11), 243–1253 (2016)
R.M. Rangayyan, Biomedical Signal Analysis: A Case-Study Approach (Wiley, Hoboken, 2002)
S.U. Rehman, A.M. Kamboh, A CMOS micro-power and area efficient neural recording and stimulation front-end for biomedical applications. Circuits Syst. Signal Process. 34(6), 1725–1746 (2015)
A. Rodriguez-Perez, J. Ruiz-Amaya, M. Delgado-Restituto, A. Rodriguez-Vazquez, A low-power programmable neural spike detection channel with embedded calibration and data compression. IEEE Trans. Biomed. Circuits Syst. 6(2), 87–100 (2012)
C. Sawigun, S. Thanapitak, A 0.9-nW, 101-Hz, and 46.3-μVrms IRN low-pass filter for ECG acquisition using FVF biquads. IEEE Trans. Very Large Scale Integr (VLSI) Syst 1–9 (2018)
R. Schreier, G.C. Temes, Understanding Delta-Sigma Data Converters (Wiley/IEEE Press, Hoboken, 2005)
S. Tao, A. Rusu, A power-efficient continuous-time incremental sigma-delta ADC for neural recording systems. IEEE Trans. Circuits Syst. I Regul. Pap. 62(6), 1489–1498 (2015)
S. Tao, A. Rusu, A comparative design study of continuous-time incremental sigma-delta ADC architectures. Int. J. Circuit Theory Appl. 44(12), 2147–2163 (2016)
S. Thanapitak, C. Sawigun, A subthreshold buffer-based biquadratic cell and its application to biopotential filter design. IEEE Trans. Circuits Syst. I Regul. Pap. 65(9), 774–2783 (2018)
T. Wu, Z. Yang, A multichannel integrated circuit for neural spike detection based on EC-PC threshold estimation, in Annual International Conference of the IEEE Engineering in Medicine and Biology Society (EMBC) (2013), pp 779–782
E. Yao, Y. Chen, A. Basu, A 0.7 V, 40 nW compact, current-mode neural spike detector in 65 nm CMOS. IEEE Trans. Biomed. Circuits Syst. 10(2), 309–318 (2016)
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This work has been financially supported by Iran National Science Foundation (INSF).
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Barati, S., Yavari, M. An Automatic Action Potential Detector for Neural Recording Implants. Circuits Syst Signal Process 38, 1923–1941 (2019). https://doi.org/10.1007/s00034-018-0969-3
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DOI: https://doi.org/10.1007/s00034-018-0969-3