Skip to main content
SpringerLink
Log in

Toward diagrammability and efficiency in event-sequence languages

  • Special section on Recent Advances in Hardware Verification
  • Published:
International Journal on Software Tools for Technology Transfer Aims and scope Submit manuscript

Abstract

Many industrial verification teams are developing suitable event-sequence languages for hardware verification. Such languages must be expressive, designer friendly, and hardware specific, as well as efficient to verify. While the formal verification community has formal models for assessing the efficiency of an event-sequence language, none of these models also accounts for designer friendliness. We propose an intermediate language for event sequences that addresses both concerns. The language achieves usability through a correlation to timing diagrams; its efficiency arises from its mapping into deterministic weak automata. We present the language, relate it to existing event-sequence languages, and prove its relationship to deterministic weak automata. These results indicate that timing diagrams can become more expressive while remaining more efficient for symbolic model checking than LTL.

This is a preview of subscription content, log in via an institution to check access.

Access this article

Log in via an institution

Price excludes VAT (USA)
Tax calculation will be finalised during checkout.

Instant access to the full article PDF.

Institutional subscriptions

Similar content being viewed by others

References

  1. Accellera Working Group. Property specification language reference manual (version 1.0) http://www.eda.org/vfv/docs/psl_lrm-1.0.pdf (2003)

  2. Amla, N., Emerson, E.A., Namjoshi, K.S.: Efficient decompositional model checking for regular timing diagrams. In: Proceedings of the IFIP Conference on Correct Hardware Design and Verification Methods (1999)

  3. Amla, N., Emerson, E.A., Namjoshi, K.S., Trefler, R.J.: Visual specifications for modular reasoning about asynchronous systems. In: Proceedings of International Conference on Formal Techniques for Networked and Distributed Systems, pp. 226–242 (2002)

  4. Armoni, R., Fix, L., Flaisher, A., Gerth, R., Ginsburg, B., Kanza, T., Landver, A., Mador-Haim, S., Singerman, E., Tiemeyer, A., Vardi, M.Y., Zbar, Y.: The ForSpec temporal logic: a new temporal property-specification language. In: Proceedings of the Conference on Tools and Algorithms for the Construction and Analysis of Systems, pp. 296–211 (2002)

  5. Bloem, R., Ravi, K., Somenzi, F.: Efficient decision procedures for model checking of linear time logic properties. In: Proceedings of the International Conference on Computer-Aided Verification. Lecture Notes in Computer Science, vol. 1633, pp. 222–235. Springer, Berlin Heidelberg New York (1999)

    Google Scholar 

  6. Bunker, A., Gopalakrishnan, G., Slind, K.: Live sequence charts applied to hardware requirements, specification, and verification: a VCI bus interface model. Int. J. Softw. Tools Technol. Transfer (2004)

  7. Cerny, E., Berkane, B., Girodias, P., Khordoc, K.: Hierarchical Annotated Action Diagrams. Kluwer, Dordrecht (1998)

    MATH  Google Scholar 

  8. Damm, W., Harel, D.: LSCs: breathing life into message sequence charts. Formal Methods Syst. Des. 19(1), 45–80 (2001)

    Article  Google Scholar 

  9. Feyerabend, K., Josko, B.: A visual formalism for real-time requirement specifications. In: Bertran, M., Rus, T. (eds.) Transformation-Based Reactive Systems Development, Proceedings of the 4th International AMAST Workshop on Real-Time Systems and Concurrent and Distributed Software (ARTS’97), vol. 1231, pp. 156–168. Springer, Berlin Heidelberg New York (1997)

    Google Scholar 

  10. Fisler, K.: Timing diagrams: formalization and algorithmic verification. J. Logic Lang. Inf. 8, 323–361 (1999)

    Article  MathSciNet  Google Scholar 

  11. Fisler, K.: On tableau constructions for timing diagrams. In: NASA Langley Formal Methods Workshop (2000)

  12. Giannakopoulou, D., Magee, J.: Fluent model checking for event-based systems. In: Proceedings of the Joint Meeting of the European Software Engineering Conference and ACM SIGSOFT Symposium on the Foundations of Software Engineering (2003)

  13. International Telecommunication Union (ITU). Message sequence chart (MSC). ITU-T Recommendation Z.120 (1993)

  14. Kupferman, O., Vardi, M.Y.: Freedom, weakness, and determinism: from linear-time to branching-time. In: Proceedings of the IEEE Symposium on Logic in Computer Science (1998)

  15. Lemon, O.: Comparing the efficacy of visual languages. In: Barker-Plummer, D., Beaver, D.I., van Benthem, J., di Luzio, P.S. (eds.) Words, Proofs, and Diagrams, pp. 47–70. CSLI Publications, Stanford, CA (2002)

    Google Scholar 

  16. Maidl, M.: The common fragment of CTL and LTL. In: Proceedings of Symposium on Foundations of Computer Science, pp. 643–652 (2000)

  17. Manna, Z., Pnueli, A.: Specification and verification of concurrent programs by ∀-automata. In: Proceedings of the ACM Symposium on Principles of Programming Languages, pp. 1–12 (1987)

  18. Oliveira, M.T., Hu, A.J.: High-level specification and automatic generation of IP interface monitors. In: Proceedings of the International Conference on Design Automation, pp. 129–134 (2002)

  19. Paun, D., Chechik, M.: Events in linear-time properties. In: Proceedings of Requirements Engineering (1999)

  20. Ramakrishna, Y., Dillon, L., Moser, L., Melliar-Smith, P., Kutty, G.: A real-time interval logic and its decision procedure. In: Proceedings of the 13th Conference on Foundations of Software Technology and Theoretical Computer Science. Lecture Notes in Computer Science, vol. 761, pp. 173–192. Springer, Berlin Heidelberg New York (1993)

    Google Scholar 

  21. Synopsys, Inc. Openvera assertions. http://www.open-vera.com/technical/technical.html (2002)

  22. Vardi, M.Y.: Branching vs. linear time: final showdown. In: Proceedings of the Conference on Tools and Algorithms for the Construction and Analysis of Systems (2001); Invited talk, European Symposium on the Theory and Practice of Software (ETAPS)

Download references

Author information

Authors and Affiliations

  1. Department of Computer Science, WPI, Worcester, MA, USA

    Kathi Fisler

Authors
  1. Kathi Fisler
    View author publications

    You can also search for this author in PubMed Google Scholar

Corresponding author

Correspondence to Kathi Fisler.

Rights and permissions

Reprints and permissions

About this article

Cite this article

Fisler, K. Toward diagrammability and efficiency in event-sequence languages. Int J Softw Tools Technol Transfer 8, 431–447 (2006). https://doi.org/10.1007/s10009-005-0195-8

Download citation

  • Published:

  • Issue Date:

  • DOI: https://doi.org/10.1007/s10009-005-0195-8

Keywords

Search

Navigation