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A dynamic zero frequency compensation for 3 A NMOS ultra-low dropout regulator

  • Mixed Signal Letter
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Abstract

A dynamic zero frequency-compensation technique for 3 A NMOS low dropout-regulator (LDO) is presented. The dynamic zero is adapted to load current to get an adequate phase margin with a load current variation from 0 to 3 A. The proposed NMOS LDO has been implemented in a standard 0.35 μm CMOS process, and the die size is as small as 650 × 890 μm2. In the experimented transient response, the load regulation of 3.3 mV/A is observed. In addition, the power-supply rejection ratio at 1 MHz can be up to −30 dB.

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References

  1. Chen, C., Wu, J. H., & Wang, Z. X. (2011). 150 mA LDO with self-adjusting frequency compensation scheme. IEE Electronics Letters, 47(13), 767–768.

    Article  MathSciNet  Google Scholar 

  2. Rincon-Mora, G. A., & Allen, P. E. (1998). A low-voltage, low quiescent current, low drop-out regulator. IEEE Journal of Solid-State Circuit, 33(1), 36–44.

    Article  Google Scholar 

  3. Gianluca, G., Gaetano, P., & Ester, S. (2012). Robust Miller compensation with current amplifiers applied to LDO voltage regulators. IEEE Transactions on Circuits and Systems, 59(9), 1880–1893.

    Article  MathSciNet  Google Scholar 

  4. Garimella, A. & Furth, P. M. (2011). Frequency compensation techniques for op-amps and LDOs: A tutorial overview. In IEEE 54th international midwest symposium on circuits and systems (MWSCAS) (pp. 1–4).

  5. Garimella, A., Surkanti, P. R. & Furth, P. M. (2012). Pole-zero analysis of low-dropout (LDO) regulators: A tutorial overview. In Proceedings of the 2012 25th international conference on VLSI Design (VLSID) (pp. 7–11).

  6. Allen, P. E. & Holberg D. R. (2002). CMOS analog circuit design, (pp. 253–269). New York: Oxford University Press.

  7. Abbasi, M. U., Bagnall, D. & Bn, V. (2010). A high PSRR capacitor-less on—Chip low dropout voltage regulator. In Proceedings of the 8th international symposium on intelligent systems and informatics Conf, Subotica, Serbia (pp. 361–364).

  8. Leung, K. N. (2003). A capacitive-free CMOS low dropout regulator with damping-factor-control compensation. IEEE Journal of Solid-State Circuit, 38(14), 1691–1702.

    Article  Google Scholar 

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Authors and Affiliations

  1. Institute of Electronic CAD, Xidian University, No, 2 South Taibai Road, Xi’an, 710071, Shaanxi, People’s Republic of China

    Guoding Dai, Chong Huang & Ling Yang

Authors
  1. Guoding Dai
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  2. Chong Huang
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  3. Ling Yang
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Correspondence to Guoding Dai.

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Dai, G., Huang, C. & Yang, L. A dynamic zero frequency compensation for 3 A NMOS ultra-low dropout regulator. Analog Integr Circ Sig Process 75, 329–333 (2013). https://doi.org/10.1007/s10470-013-0060-8

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  • DOI: https://doi.org/10.1007/s10470-013-0060-8

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