A 2GS/s 6-bit CMOS time-interleaved ADC for analysis of mixed-signal calibration techniques

Abstract

A 2-GS/s 6-bit time interleaved (TI) successive approximation register (SAR) analog-to-digital converter (ADC) is designed and fabricated in a 0.13 $\upmu$m CMOS process. The architecture uses 8 time-interleaved track-and-hold amplifiers (THA) and 16 asynchronous SAR ADCs. The sampling frequency of the TI-ADC can be set from 200 MHz to more than 2 GHz. The chip includes a programmable delay cell array to adjust up to $\pm$25 % the sampling clock phase in each THA, and a multi-channel low voltage differential signaling interface capable of transmitting at full sampling rate ($\geqslant$12 Gb/s), without decimation, off-chip. These blocks make the fabricated ADC an excellent platform to test/evaluate mixed-signal calibration algorithms, which are of great interest for application in high-speed optical systems. Measurements of the fabricated ADC show a peak signal-to-noise-and-distortion ratio of 33.9 dB and a power consumption of 192 mW at 1.2 V.

Appendix: Metastability analisys in SAR ADCs

The metastability has been widely studied in the past literature (e.g., see [10, 21, 34]). The probability of a metastable state in a comparator is given by [10, 34]

$$\begin{aligned} P_ c \cong \dfrac{2 V_{logic} e^{(-T_ {reg} /\tau })}{A_ {Pre} V_ {FS }} \end{aligned}$$

(1)

where $V _{logic}$ is the power voltage used in the comparator, $T _{reg}$ is the time available for latch regeneration, $\tau$ is the time constant at the regeneration latch output ($\tau \approx g_m /C$), $A _{Pre}$ is the comparator pre-amplifier gain, and $V _{FS}$ is the maximum differential swing at the comparator inputs.

For a conventional N-bit SAR-ADC, the probability of a metastable state (or conversion error rate) in a complete conversion cycle can be estimated considering that $V_ {FS}$ is reduced by half after each subcycle. Then, the probability of a metastable event after N subcycles results in

$$\begin{aligned} P_ M & = & {} 2^0 P_ c + \cdots + 2^ {N-1} P_ {c} , \end{aligned}$$

(2)

$$\begin{aligned}\,= \,& {} (2^ N -1)P_ c . \end{aligned}$$

(3)

Assuming that $2^N \gg 1$, we get

$$\begin{aligned} P_ M \approx 2^ N P_ c = 2^ N \alpha e^{(-T_ {reg} /\tau )}, \end{aligned}$$

(4)

where $\alpha = (2 V_ {logic} )/({A_ {Pre} V_ {FS }})$. Note that the conversion error rate (4) is similar to the one achieved by a Flash ADC as deduced in [10]. In order to obtain a low error conversion rate, the ratio $(T_ {reg} /\tau )$ should be maximized. Since $\tau$ is a constant constrained by the technology process, note that the maximum value of $T_ {reg}$ shall be determined by the desired conversion error rate, that is,

$$\begin{aligned} T_{reg} = \tau \left[ -ln\left( P_{M} \right) + ln \left( 2^{N} \alpha \right) \right] . \end{aligned}$$

(5)

For a given value of $P_M$, the sampling period of a synchronous SAR (S-SAR) is

$$\begin{aligned} T_{S-SAR} \approx T_ t + N(T_ {reg} +T_ {Logic} +T_ {{DAC}{set}} ), \end{aligned}$$

(6)

where $T_{t}$ is the DAC tracking time, $T_{Logic}$ is the clock to DAC switch propagation delay, and $T_ {{DAC}_{set}}$ is the DAC settling time. On the other hand, for an asynchronous SAR (A-SAR) topology, the minimum sampling period is given by

$$\begin{aligned} T_{A-SAR} \approx T_{t} + T_{reg} + M\tau + N(T_{C2DAC}+T_{{DAC}{set}}), \end{aligned}$$

(7)

where $T_{reg}$ is the extra time considered for a metastable state resolution and $T_{C2DAC}$ is the propagation delay from ready signal to DAC switch; term $M\tau$ is the total regeneration time required for all the asynchronous SAR approximation cycles (without considering a metastable state) where M is given by [7]:

$$\begin{aligned} M \approx N^2 ln(2) - (N/2)(N-1)ln(2) \end{aligned}$$

(8)

Parameters $\tau$, $\alpha$, $T_{DAC_{set}}$, $T_{t}$, and $T_{C2DAC}$ have been derived from Spice simulations results for 130 $\upmu$m CMOS technology. Finally, curves in Fig. 4 are easily derived from (5), (6), and (7).