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System-level design based on UML/MARTE for FPGA-based embedded real-time systems

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Abstract

This paper discusses an approach to generate VHDL descriptions from high-level specifications, namely UML/MARTE models that include aspect-oriented semantics. Standard UML diagrams describe the handling of functional requirements, whereas crosscutting concerns associated with the non-functional requirements are handled by aspects. UML-to-VHDL transformation is performed automatically by a script-based code generation tool named GenERTiCA. For that, mapping rules scripts define how to generate VHDL constructs from model elements, including the implementation of aspects adaptations. The generated VHDL description does not require any manual modification, in order to be fully synthesized onto a FPGA device. Some case studies have been performed to evaluate the proposed approach, including examples of real systems implemented as a FPGA-based embedded system. Obtained results show an improvement in system design in terms of an increase in system performance as well as a better utilization of FPGA reconfigurable resources. Such positive results are related to a better modularization of components achieved by using the proposed high-level approach. These case studies demonstrate the practicability of full translation of platform-independent specifications into VHDL descriptions.

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Notes

  1. In this text, a “method” encapsulates a behavior of the object that is executed in response to a message sent from other object.

  2. The generated VHDL description was synthesized, uploaded and executed on a FPGA development kit without any manual modification.

  3. E.g. model, source code, description of components, etc.

  4. Such a behavior is a limitation of the used FPGA development board.

  5. In a synchronous method call, the execution of caller method stops when the method call occurs and continues only after the called method finishes its execution; in an asynchronous method call, the caller method continues executing its behavior after the method call, and the called method executes its behavior in parallel.

  6. An active object executes autonomously its behaviors in parallel with other active objects. A passive object only execute its behaviors in response to method calls from other objects.

  7. This new aspect has been proposed in this work.

  8. Such a component must be an IP available in the library of the chosen FPGA platform.

  9. 300 % increase in IOB metric in V2 was included in this average amount.

  10. i.e. mapping rules scripts for these adaptations have been completely written once.

  11. The case studies presented in [32] are: (i) the movement control of an unmanned helicopter; (ii) the control systems of an industrial packing system; and (iii) the control system of an electric wheelchair. Those systems are larger and more complex than the ones presented here.

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Acknowledgments

This work is supported by National Council for Scientific and Technological Development (CNPq-Brazil) through the Grant 480321/2011-6.

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Authors and Affiliations

  1. Instituto Federal Catarinense (IFC Araquari), Araquari, Brazil

    Marcela Leite

  2. Federal University of Technology - Paraná (UTFPR), Curitiba, Brazil

    Marco Aurélio Wehrmeister

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  1. Marcela Leite
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  2. Marco Aurélio Wehrmeister
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Correspondence to Marco Aurélio Wehrmeister.

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Leite, M., Wehrmeister, M.A. System-level design based on UML/MARTE for FPGA-based embedded real-time systems. Des Autom Embed Syst 20, 127–153 (2016). https://doi.org/10.1007/s10617-016-9172-6

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