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Analysis of electrostatic doped Schottky barrier carbon nanotube FET for low power applications

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Abstract

This paper presents the analysis of electrostatic doped Schottky barrier carbon nanotube FET (ED-SBCNTFET) for low power applications. Electrostatic doping is introduced in intrinsic CNT as a channel material which reduces the process complexity; moreover dynamic configuration provides symmetric transfer characteristics for n-type and p-type for ED-SBCNTFET. Simulation results demonstrate that ED-SBCNTFET is better than conventional CNTFET in terms of IOFF and subthreshold swing (SS) which makes it suitable for low power applications. Simulations are performed and sensitivity analysis is carried out for CNT diameter, effective oxide thickness (EOT), high-k dielectric and polarity gate bias. It is observed that CNTs are most sensitive to diameter, since CNT with diameter 0.85 nm exhibits ION/IOFF ratio of ~109 and SS of 60.8 mv/dec whereas diameter of 0.55 nm results into ION/IOFF ratio of ~1011 with SS of 58.5 mv/dec. Optimized parameters are proposed for low power applications in terms of IOFF and SS. ED-SBCNTFET has been analysed for various process parameters and it has been demonstrated to be less sensitive to process variations.

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References

  1. P.L. McEuen, M.S. Fuhrer, H. Park, Single-walled carbon nanotube electronics. IEEE Trans. Nanotechnol. 1(1), 78–85 (2002)

    Article  Google Scholar 

  2. T. Dürkop, S.A. Getty, E. Cobas, M.S. Fuhrer, Extraordinary mobility in semiconducting carbon nanotubes. Nano Lett. 4(1), 35–39 (2004)

    Article  Google Scholar 

  3. Ali Javey, Jing Guo, Qian Wang, Mark Lundstrom, Hongjie Dai, Ballistic carbon nanotube field-effect transistors. Nature 424(6949), 654–657 (2003)

    Article  Google Scholar 

  4. P.L. McEuen, M.S. Fuhrer, H. Park, Single-walled carbon nanotube electronics. IEEE Trans. Nanotechnol. 1(1), 78–85 (2002)

    Article  Google Scholar 

  5. J. Svensson, E.B. Campbell, Schottky barriers in carbon nanotube-metal contacts. J. Appl. Phys. 110(11), 111101-1–111101-16 (2011)

    Article  Google Scholar 

  6. Joerg Appenzeller, Comparing carbon nanotube transistors—the ideal choice: a novel tunneling device design. IEEE Trans. on Electron Devices 52(12), 2568–2576 (2005)

    Article  Google Scholar 

  7. Y.-M. Lin, J. Appenzeller, J. Knoch, P. Avouris, High performance carbon nanotube field-effect transistor with tunable polarities. IEEE Trans. on Nanotechnol. 4(5), 481–489 (2005)

    Article  Google Scholar 

  8. A. Javey, R. Tu, D. Farmer, J. Guo, R. Gordon, H. Dai, High performance n-type carbon nanotube field-effect transistors with chemically doped contacts. Nano Lett. 5(2), 345–348 (2005)

    Article  Google Scholar 

  9. J. Knoch, M.R. Muller, Electrostatic Doping—Controlling the Properties of Carbon-Based FETs With Gates. IEEE Trans. on Nanotechnol. 13(6), 1044–1052 (2014)

    Article  Google Scholar 

  10. A. Lahgere, C. Sahu, J. Singh, PVT-aware design of dopingless dynamically configurable tunnel FET. IEEE Trans. on Electron Devices 62(8), 2404–2409 (2015)

    Article  Google Scholar 

  11. Sangeeta Singh, P.N. Kondekar, A novel dynamically configurable electrostatically doped silicon nanowire impact ionization MOS. Superlattices and Microstruct. 88, 695–703 (2015)

    Article  Google Scholar 

  12. K. Roy, S. Mukhopadhyay, H. Mahmoodi-Meimand, Leakage current mechanisms and leakage reduction techniques in deep-submicrometer CMOS circuits. Proc. of the IEEE 91(2), 305–327 (2003)

    Article  Google Scholar 

  13. V.K. Sharma, M. Pattanaik, B. Raj, PVT variations aware low leakage INDEP approach for nanoscale CMOS Circuits. Microelectron. Reliab. 54, 90–99 (2014)

    Article  Google Scholar 

  14. V.K. Sharma, M. Pattanaik, Balwinder Raj, INDEP approach for leakage reduction in nanoscale CMOS circuits. Int. J. Electron., Taylor & Francis 102(2), 200–215 (2015)

    Google Scholar 

  15. Amandeep Singh, Mamta Khosla, Balwinder Raj, Comparative Analysis of Carbon Nanotube Field Effect Transistor and Nanowire Transistor for Low Power Circuit Design. J. Nanoelectron. and Optoelectron. 11(3), 388–393 (2016)

    Article  Google Scholar 

  16. Karmjit Singh, Balwinder Raj, Influence of temperature on MWCNT bundle, SWCNT bundle and copper interconnects for nanoscaled technology nodes. J. Mater. Sci.: Mater. in Electron. 26(8), 6134–6142 (2015)

    Google Scholar 

  17. G. Fiori, G. Iannaccone, NanoTCAD ViDES, 2008

  18. Amandeep Singh, Mamta Khosla, Balwinder Raj, Circuit compatible model for Electrostatic Doped Schottky Barrier CNTFET. J. Electron. Mater. 45(10), 5381–5390 (2016)

    Article  Google Scholar 

  19. X. Yang, K. Mohanram, Modeling and performance investigation of the double-gate carbon nanotube transistor. IEEE Electron Device Lett. 32(3), 231–233 (2011)

    Article  Google Scholar 

  20. J. Guo, S. Datta, M. Lundstrom, M. Brink, P. McEuen, A. Javey, H. Dai, H. Kim, P. McIntyre, Assessment of silicon MOS and carbon nanotube FET performance limits using a general theory of ballistic transistors. Electron Devices Meeting, 2002. IEDM ‘02. Int. 711–714 (2002)

  21. Sujeet Kumar Sinha, Santanu Chaudhury, Impact of oxide thickness on gate capacitance—a comprehensive analysis on MOSFET, nanowire FET, and CNTFET devices. IEEE Trans. on Nanotechnol. 12(6), 958–964 (2013)

    Article  Google Scholar 

  22. A. Javey, H. Kim, M. Brink, Q. Wang, A. Ural, J. Guo, P. McIntyre, P. McEuen, M. Lundstrom, H. Dai, High K dielectrics for advanced carbon nanotube transistors and logic. Nature Mater. 1(4), 241–246 (2002)

    Article  Google Scholar 

  23. J. Deng, H.S.P. Wong, A compact SPICE model for carbon-nanotube field-effect transistors including nonidealities and its application—Part I: model of the intrinsic channel region. IEEE Trans. on Electron Devices 54(12), 3186–3194 (2007)

    Article  Google Scholar 

  24. J. Deng, H.S.P. Wong, A compact SPICE model for carbon-nanotube field-effect transistors including nonidealities and its application—Part II: full device model and circuit performance benchmarking. IEEE Trans. on Electron Devices 54(12), 3195–3205 (2007)

    Article  Google Scholar 

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Authors and Affiliations

  1. Department of Electronics and Communication, National Institute of Technology, Jalandhar, Punjab, 144011, India

    Amandeep Singh, Mamta Khosla & Balwinder Raj

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  1. Amandeep Singh
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  2. Mamta Khosla
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  3. Balwinder Raj
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Correspondence to Amandeep Singh.

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Singh, A., Khosla, M. & Raj, B. Analysis of electrostatic doped Schottky barrier carbon nanotube FET for low power applications. J Mater Sci: Mater Electron 28, 1762–1768 (2017). https://doi.org/10.1007/s10854-016-5723-7

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  • DOI: https://doi.org/10.1007/s10854-016-5723-7

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