Abstract
Modular exponentiation is an essential arithmetic operation for various applications, such as cryptography. The performance of this operation has a tremendous impact on the efficiency of the whole application. Therefore, many researchers devoted special interest to providing smart methods and efficient implementations for that operation. One of these methods is the sliding-window method, which pre-processes the exponent into zero and non-zero partitions. Zero partitions allow for a reduction of the number of modular multiplications required in the exponentiation process. In this paper, we devise two novel hardware designs for computing modular exponentiation using the sliding-window method: one uses the constant-length non-zero partitions strategy (CLNZ) and the other uses the variable-length non-zero partitions strategy (VLNZ). The implementations are compared to existing hardware implementations of the modular exponentiation in terms of hardware area, time and throughput requirements.
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Acknowledgements
We are grateful to the reviewers and the editor that contributed to the great improvement of the original version of this paper with their valuable comments and suggestions. We also are thankful to FAPERJ (Fundação de Amparo à Pesquisa do Estado do Rio de Janeiro, http://www.faperj.br) and CNPq (Conselho Nacional de Desenvolvimento Científico e Tecnológico, http://www.cnpq.br) for their continuous financial support.
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Nedjah, N., de Macedo Mourelle, L. High-throughput cryptographic system using window-based modular exponentiation for secure communications. Telecommun Syst 54, 345–357 (2013). https://doi.org/10.1007/s11235-013-9738-6
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DOI: https://doi.org/10.1007/s11235-013-9738-6