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Designing a Posture Analysis System with Hardware Implementation

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Abstract

Posture analysis is an active research area in computer vision for applications such as home care and security monitoring. This paper describes the design of a system for posture analysis with hardware acceleration, addressing the following four aspects: (a) a design workflow for posture analysis based on radial shape and projection histogram representations; (b) the implementation of different architectures based on a high-level hardware design approach with support for automating transformations to improve parallelism and resource optimisation; (c) accuracy evaluation of the proposed posture analysis system, and (d) performance evaluation for the derived designs. One of the designs, which targets a Xilinx XC2V6000 FPGA at 90.2 MHz, is able to perform posture analysis at a rate of 1,164 frames per second with a frame size of 320 by 240 pixels. It represents 3.5 times speedup over optimised software running on a 2.4 GHz AMD Athlon 64 3700+ computer. The frame rate is well above that of real-time video, which enables the sharing of the FPGA among multiple video sources.

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Acknowledgements

The support of DTI Next Wave Programme, Fundação para a Ciência e Tecnologia (Grant number SFRH/BD/3354/2000), UK Engineering and Physical Sciences Research Council (Grant number EP/C 509625/1 and EP/C 549481/1), Celoxica Limited and Xilinx, Inc. is gratefully acknowledged. Furthermore, we thank the reviewers for their useful suggestions.

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Authors and Affiliations

  1. Department of Computing, Imperial College London, 180 Queen’s Gate, London, SW7 2EZ, UK

    J. G. F. Coutinho, M. P. T. Juvonen, J. L. Wang, B. L. Lo, W. Luk, O. Mencer & G. Z. Yang

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  1. J. G. F. Coutinho
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  2. M. P. T. Juvonen
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  3. J. L. Wang
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  4. B. L. Lo
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  5. W. Luk
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  6. O. Mencer
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  7. G. Z. Yang
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Correspondence to J. G. F. Coutinho.

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Coutinho, J.G.F., Juvonen, M.P.T., Wang, J.L. et al. Designing a Posture Analysis System with Hardware Implementation. J VLSI Sign Process Syst Sign Image Video Technol 47, 33–45 (2007). https://doi.org/10.1007/s11265-006-0016-7

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  • DOI: https://doi.org/10.1007/s11265-006-0016-7

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