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An Improved Logarithmic Multiplier for Media Processing

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Abstract

As the modern computing systems become increasingly embedded and portable, a growing set of applications in media processing (graphics, audio, video, and image) has evolved. Multiplication is the operation that is most often used in these applications which when accomplished in logarithmic number system results in an area efficient and faster design. In this work, the authors describe a technique that combines Mitchell’s approximation with a novel hardware truncation scheme resulting in an iterative multiplier with improved precision and reduced area. Further, a new fractional predictor combined with an existing truncated logarithmic shifter significantly reduces the overall hardware cost of the multiplier. Simulations carried out on benchmark image processing applications such as Lena, cameraman and pirate clearly indicate that the proposed technique performs better than those available in the literature.

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Authors and Affiliations

  1. Electrical Department, BITS Pilani, Hyderabad Campus, Hyderabad, India

    Syed Ershad Ahmed

  2. School of Engineering and Technology, BML Munjal University, Gurgaon, India

    M. B. Srinivas

Authors
  1. Syed Ershad Ahmed
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  2. M. B. Srinivas
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Correspondence to Syed Ershad Ahmed.

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Ahmed, S.E., Srinivas, M.B. An Improved Logarithmic Multiplier for Media Processing. J Sign Process Syst 91, 561–574 (2019). https://doi.org/10.1007/s11265-018-1350-2

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  • DOI: https://doi.org/10.1007/s11265-018-1350-2

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