Skip to main content
SpringerLink
Log in

Strained Si on Insulator as Potential Material for Forced Stacked Multi-threshold FinFET Based Inverter Considering Ultra Low-Power Applications

  • Regular Paper
  • Published:
Transactions on Electrical and Electronic Materials Aims and scope Submit manuscript

Abstract

This work investigates the performance of strained Si on insulator as potential material for forced stacked multi-threshold FinFET based inverter considering its ultra low-power applications. Using the calibrated exhaustive 3D-TCAD mixed-mode simulation a comparative analysis of conventional and forced stack FinFET based inverters has been performed. The static and dynamic characteristics have been compared with conventional and forced stacked FinFET based inverter. The leakage in standby mode can be reduced through well-defined stack and multi-threshold (VTH) transistors. Channel doping is optimized to get higher VTH devices. To improve the speed of circuits FinFETs are designed on strained Silicon on Insulator (sSOI) wafer. Uniform uniaxial tensile stress in sSOI gives the advantage of high ON current in n-FinFETs. It is observed that using strained FinFETs the maximum delay is reduced below 10 ps and using multi VTH forced stack technique the leakage power is reduced. Hence, forced stack technique based FinFET can evolve as a potential candidate for the future ultra-low power device applications.

This is a preview of subscription content, log in via an institution to check access.

Access this article

Log in via an institution

Price excludes VAT (USA)
Tax calculation will be finalised during checkout.

Instant access to the full article PDF.

Institutional subscriptions

Fig. 1
Fig. 2
Fig. 3
Fig. 4
Fig. 5
Fig. 6
Fig. 7
Fig. 8
Fig. 9

Similar content being viewed by others

References

  1. S.G. Narendra, A. Chandrakasan, Leakage in Nanometer Technologies (Springer, New York, 2006)

  2. T. Skotnicki, J.A. Hutchby, T.-J. King, H.S.P. Wong, F. Boeuf, IEEE Circuits Devices Mag. 21(1), 16–26 (2005)

    Article  Google Scholar 

  3. G. Pei, J. Kedzierski, P. Oldiges, M. Ieong, E.-C. Kan, IEEE Trans. Electron Devices 49(8), 1411–1419 (2002)

    Article  Google Scholar 

  4. Y. Li, C.-H. Hwang, IEEE Trans. Electron Devices 54(12), 3426–3429 (2007)

    Article  Google Scholar 

  5. W. Xiong, C. Cleavelin, P. Kohli, C. Huffman, T. Schulz, K. Schruefer, G. Gebara, K. Mathews, P. Patruno, Y.-M. Le Vaillant, I. Cayrefourcq, M. Kennard, C. Mazure, K. Shin, T.-J. Liu, IEEE Electron Device Lett. 27(7), 612–614 (2006)

    Article  Google Scholar 

  6. Y. Jiang, T. Liow, N. Singh, L. Tan, G. Lo, D. Chan, D. Kwong, Symposium on VLSI Technology (2008), pp. 34–35

  7. E. Ungersboeck, V. Sverdlov, H. Kosina, S. Selberherr, 8th International Conference on Solid-State and Integrated Circuit Technology (2006), pp. 124-127

  8. J.-S. Lim, S. Thompson, J. Fossum, IEEE Electron Device Lett. 25(11), 731–733 (2004)

    Article  Google Scholar 

  9. T. Mizuno, S. Takagi, N. Sugiyama, H. Satake, A. Kurobe, A. Toriumi, IEEE Electron Device Lett. 21(5), 230–232 (2000)

    Article  Google Scholar 

  10. S.E. Thompson, M. Armstrong, C. Auth, M. Alavi, M. Buehler, R. Chau, S. Cea, T. Ghani, G. Glass, T. Hoffman, C.H. Jan, C. Kenyon, J. Klaus, K. Kuhn, Z. Ma, B. Mcintyre, K. Mistry, A. Murthy, B. Obradovic, R. Nagisetty, P. Nguyen, S. Sivakumar, R. Shaheed, L. Shifren, B. Tufts, S. Tyagi, M. Bohr, Y. El-Mansy, IEEE Trans. Electron Devices 51(11), 1790–1797 (2004)

    Article  Google Scholar 

  11. N. Collaert, A.D. Keersgieter, K.G. Anil, R. Rooyackers, G. Eneman, M. Goodwin, B. Eyckens, E. Sleeckx, J.F. de Marneffe, K.D. Meyer, P. Absil, M. Jurczak, S. Biesemans, IEEE Electron Device Lett. 26(11), 820–822 (2005)

    Article  Google Scholar 

  12. C. Auth, A. Cappellani, J. S. Chun, A. Dalis, A. Davis, T. Ghani, G. Glass, T. Glassman, M. Harper, M. Hattendorf, P. Hentges, S. Jaloviar, S. Joshi, J. Klaus, K. Kuhn, D. Lavric, M. Lu, H. Mariappan, K. Mistry, B. Norris, N. Rahhal-orabi, P. Ranade, J. Sandford, L. Shifren, V. Souw, K. Tone, F. Tambwe, A. Thompson, D. Towner, T. Troeger, P. Vandervoorn, C. Wallace, J. Wiedemer, C. Wiegand, Symposium on VLSI Technology (2008), pp. 128–129

  13. K. Maitra, A. Khakifirooz, P. Kulkarni, V.S. Basker, J. Faltermeier, H. Jagannathan, H. Adhikari, C.C. Yeh, N.R. Klymko, K. Saenger, T. Standaert, R.J. Miller, B. Doris, V.K. Paruchuri, D. McHerron, J. ONeil, E. Leobundung, H. Bu, IEEE Electron Device Lett. 32(6), 713–715 (2011)

    Article  Google Scholar 

  14. S. Narendra, V. De, S. Borkar, D.A. Antoniadis, A.P. Chandrakasan, IEEE J. Solid State Circuits 39(3), 501–510 (2004)

    Article  Google Scholar 

  15. S. Mutoh, T. Douseki, Y. Matsuya, T. Aoki, S. Shigematsu, J. Yamada, IEEE J. Solid State Circuits 30(8), 847–854 (1995)

    Article  Google Scholar 

  16. D. Baccarin, D. Esseni, M. Alioto, IEEE Trans. Very Large Scale Integr. VLSI Syst. 20(8), 1467–1472 (2012)

    Article  Google Scholar 

  17. C.H. Lin, R. Kambhampati, R.J. Miller, T.B. Hook, A. Bryant, W. Haensch, P. Oldiges, I. Lauer, T. Yamashita, V. Basker, T. Standaert, K. Rim, E. Leobandung, H. Bu, M. Khare, Symposium on VLSI Technology (2012), pp. 15–16

  18. Sentaurus Process User Guide, Version I-2013.12, Synopsys Co., Mountain View, CA. (2013)

  19. Sentaurus Device User Guide, Version I-2013.12, Synopsys Co., Mountain View, CA (2013)

  20. S. Dubey, P.N. Kondekar, Microelectron. Eng. 162, 63–68 (2016)

    Article  Google Scholar 

  21. S. Dubey, P.N. Kondekar, Microelectron. J. 55, 108–115 (2016)

    Article  Google Scholar 

  22. S. Dubey, P.N. Kondekar, IEEE 3rd International Conference on Emerging Electronics (ICEE) (2016), pp. 1–4

  23. S. Dubey, P.N. Kondekar, Superlattices Microstruct. 102, 74–78 (2017)

    Article  Google Scholar 

  24. S. Singh, P.N. Kondekar, J. Comput. Electron. 16(3), 685–695 (2017)

    Article  Google Scholar 

  25. N. Collaert, R. Rooyackers, A.D. Keersgieter, F.E. Leys, I. Cayrefourcq, B. Ghyselen, R. Loo, M. Jurczak, IEEE Electron Device Lett. 28(7), 646–648 (2007)

    Article  Google Scholar 

  26. A.B. Sachid, C. Hu, International Symposium on VLSI Technology, Systems and Application (VLSI-TSA) (2014), pp. 1–2

  27. P. Mishra, A. Muttreja, N.K. Jha, FinFET Circuit Design (Springer, New York, 2011), pp. 23–54

    Google Scholar 

  28. N. Serra, F. Conzatti, D. Esseni, M. De Michielis, P. Palestri, L. Selmi, S. Thomas, T.E. Whall, E.H.C. Parker, D.R. Leadley, L. Witters, IEEE International Electron Devices Meeting (IEDM) (2009), pp. 1–4

  29. T. Hemert, B.K. Kemaneci, R.J.E. Hueting, D. Esseni, M.J.H van Dal, J. Schmitz, IEEE Solid-State Device Research Conference (ESSDERC) (2011), pp. 275–278

  30. T. Wang, X. Cui, Y. Ni, D. Yu, X. Cui, IEEE Trans. Very Large Scale Integr. VLSI Syst. 99, 1–8 (2018)

    Google Scholar 

  31. M.S. Yeh, G.L. Luo, F.J. Hou, P.J. Sung, C.J. Wang, C.J. Su, C.T. Wu, Y.C. Huang, T.C. Hong, B.Y. Chen, K.M. Chen, IEEE J. Electron Devices Soc. 6, 1232–1237 (2018)

    Google Scholar 

  32. T. Cui, J. Li, Y. Wang, S. Nazarian, M. Pedram, IEEE Trans. Emerg. Top. Comput. 6(2), 172–183 (2018)

    Article  Google Scholar 

Download references

Author information

Authors and Affiliations

  1. Microelectronics and VLSI Lab., National Institute of Technology, Patna, 800005, India

    Sangeeta Singh & Saurabh Kharwar

  2. Department of Electronics and Communication Engineering, IIITDM, Jabalpur, India

    Shashank Dubey & P. N. Kondekar

Authors
  1. Sangeeta Singh
    View author publications

    You can also search for this author in PubMed Google Scholar

  2. Shashank Dubey
    View author publications

    You can also search for this author in PubMed Google Scholar

  3. Saurabh Kharwar
    View author publications

    You can also search for this author in PubMed Google Scholar

  4. P. N. Kondekar
    View author publications

    You can also search for this author in PubMed Google Scholar

Corresponding author

Correspondence to Sangeeta Singh.

Additional information

Publisher's Note

Springer Nature remains neutral with regard to jurisdictional claims in published maps and institutional affiliations.

Rights and permissions

Reprints and permissions

About this article

Check for updates. Verify currency and authenticity via CrossMark

Cite this article

Singh, S., Dubey, S., Kharwar, S. et al. Strained Si on Insulator as Potential Material for Forced Stacked Multi-threshold FinFET Based Inverter Considering Ultra Low-Power Applications. Trans. Electr. Electron. Mater. 20, 364–370 (2019). https://doi.org/10.1007/s42341-019-00118-6

Download citation

  • Received:

  • Revised:

  • Accepted:

  • Published:

  • Issue Date:

  • DOI: https://doi.org/10.1007/s42341-019-00118-6

Keywords

Search

Navigation