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A Low-Loss Built-In Current Sensor

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Abstract

This paper presents a novel built-in current sensor that uses two additional power supply voltages besides the system power supply voltage, and that is constructed by using a current mirror circuit to pick up an abnormal IDDQ. It is activated only by an abnormal quiescent power supply current and minimizes the voltage drop at the terminal of the circuit under test. Simulation results showed that it could detect 16-μA IDDQ against 0.03-V voltage drop at 3.3-V VDD and that it reduced performance degradation in the circuit under test. It is therefore suitable for testing low-voltage integrated circuits. Moreover, we verified the behavior of the sensor circuit implemented on the board by using discrete devices. Experimental results showed that the real circuit of the sensor functioned properly.

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References

  1. M. Levi, “CMOS is Most Testable,” Proc. Int. Test Conf., 1981, pp. 217–220.

  2. J.M. Soden, C.F. Hawkins, R.K. Gulati, and W. Mao, “IDDQ Testing: A Review,” Journal of Electronic Testing: Theory and Applications, Vol. 3, No. 4, pp. 291–303, Dec. 1992.

    Google Scholar 

  3. S. Chakravarty and P.J. Thadikaran, Introduction to IDDQ Testing, Kluwer Academic Publishers, 1997.

  4. C.F. Hawkins, J.M. Soden, A.W. Righter, and F.J. Ferguson, “Defect Classes--An Overdue Paradigm for CMOSIC Testing,” Proc. Int. Test Conf., 1994, pp. 413–425.

  5. A.D. Singh, H. Rasheed, and W.W. Weber, “IDDQ Testing of CMOS Opens: An Experimental Study,” Proc. Int. Test Conf., 1995, pp. 479–489.

  6. A.W. Righter, J.M. Soden, and R.W. Beegle, “High Resolution IDDQ Characterization and Testing--Practical Issues,” Proc. Int. Test Conf., 1996, pp. 259–268.

  7. J. van Sas, V. Swerts, and M. Darquennes, “Towards an Effective IDDQ Test Vector Selection and Application Methodology,” Proc. Int. Test Conf., 1996, pp. 491–500.

  8. T.J. Powell, J.R. Pair, and B.G. Carbajal III, “Correlating Defects to Functional and IDDQ Tests,” Proc. Int. Test Conf., 1996, pp. 501–510.

  9. F. Peters and S. Oostdijk, “Realistic Defect Coverage of Voltage and Current Test,” Proc. IDDQ Workshop, 1996, pp. 4–8.

  10. T.C. Ibrahim, N. Hajj, E.M. Rudnick, and J.H. Patel, “An Efficient IDDQ Test Generation Scheme for Bridging Faults in CMOS Digital Circuits,” Proc. IDDQ Workshop, 1996, pp. 74–78.

  11. W. Maly and P. Nigh, “Built-in Current Testing--Feasibility Study,” Proc. Int. Conf. Circuit-Aided Design, 1988, pp. 340–343.

  12. Y. Miura and K. Kinoshita, “Circuit Design for Built-in Current Testing,” Proc. Int. Test Conf., 1992, pp. 873–881.

  13. J. Argüelle, M. Martinez, and S. Bracho, “Dynamic Idd Test Circuit for Mixed Signal ICs,” Electronics Letters, Vol. 30, No. 6, pp. 485–486, March 1994.

    Google Scholar 

  14. T.-L. Shen, J.C. Daly, and J.-C. Lo, “A 2-ns Detecting Time, 2 μm CMOS Built-in Current Sensing Circuit,” IEEE J. Solid-State Circuits, Vol. 28, No. 1, pp. 72–77, Jan. 1993.

    Google Scholar 

  15. J.-J. Tang, K.-J. Lee, and B.-D. Liu, “A Practical Current Sensing Technique for IDDQ Testing,” IEEE Trans. VLSI Systems, Vol. 3, No. 2, pp. 302–310, June 1995.

    Google Scholar 

  16. S.P. Athan, D.L. Landis, and S.A. Al-Arian, “A Novel Built-in Current Sensor for IDDQ Testing of Deep Submicron CMOS ICs,” Proc. VLSI Test Symp., 1996, pp. 118–123.

  17. C.-W. Lu, C.L. Lee, and J.-E. Chen, “A Fast and Sensitive Builtin Current Sensor for IDDQ Testing,” Proc. IDDQ Workshop, 1996, pp. 56–58.

  18. K. Arabi and B. Kaminska, “Design and Realization of an Accurate Built-in Current Sensor for On-Line Power Dissipation Measurement and IDDQ Testing,” Proc. Int. Test Conf., 1997, pp. 578–586.

  19. T.-C. Huang, M.-C. Huang, and K.-J. Lee, “A High-Speed Low-Voltage Built-in Current Sensor,” Proc. IDDQ Workshop, 1997, pp. 90–94.

  20. Y. Miura, “An IDDQ Sensor Circuit for Low-Voltage ICs,” Proc. Int. Test Conf., 1997, pp. 938–947

  21. N. Weste and K. Eshraghian, Principles of CMOS VLSI Design: A System Perspective, chap. 4, Addison Wesley, MA, 1985.

    Google Scholar 

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Miura, Y., Yamazaki, H. A Low-Loss Built-In Current Sensor. Journal of Electronic Testing 14, 39–48 (1999). https://doi.org/10.1023/A:1008393104650

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  • DOI: https://doi.org/10.1023/A:1008393104650

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