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On-Line Techniques for Error Detection and Correction in Processor Registers with Cross-Parity Check

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Abstract

This paper proposes the Cross-Parity check as a method for an on-line detection of multiple bit-errors in registers or register files of microprocessors. Transient or ‘soft’ errors caused by radiation as single event upsets (SEUs) or electromagnetic coupling are in the focus of this work. Especially for register files or register groups, an easy implementable error correction method is proposed, which can be implemented by software routines or additional hardware. The method is based on the logical interpretation of Cross-Parity vectors.

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Pflanz, M., Walther, K., Galke, C. et al. On-Line Techniques for Error Detection and Correction in Processor Registers with Cross-Parity Check. Journal of Electronic Testing 19, 501–510 (2003). https://doi.org/10.1023/A:1025165712071

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  • DOI: https://doi.org/10.1023/A:1025165712071

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