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Modeling of Electrical Overstress in Integrated Circuits

  • Book
  • © 1995

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Part of the book series: The Springer International Series in Engineering and Computer Science (SECS, volume 289)

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Table of contents (9 chapters)

Keywords

About this book

Electrical overstress (EOS) and Electrostatic discharge (ESD) pose one of the most dominant threats to integrated circuits (ICs). These reliability concerns are becoming more serious with the downward scaling of device feature sizes. Modeling of Electrical Overstress in Integrated Circuits presents a comprehensive analysis of EOS/ESD-related failures in I/O protection devices in integrated circuits.
The design of I/O protection circuits has been done in a hit-or-miss way due to the lack of systematic analysis tools and concrete design guidelines. In general, the development of on-chip protection structures is a lengthy expensive iterative process that involves tester design, fabrication, testing and redesign. When the technology is changed, the same process has to be repeated almost entirely. This can be attributed to the lack of efficient CAD tools capable of simulating the device behavior up to the onset of failure which is a 3-D electrothermal problem. For these reasons, it is important to develop and use an adequate measure of the EOS robustness of integrated circuits in order to address the on-chip EOS protection issue. Fundamental understanding of the physical phenomena leading to device failures under ESD/EOS events is needed for the development of device models and CAD tools that can efficiently describe the device behavior up to the onset of thermal failure.
Modeling of Electrical Overstress in Integrated Circuits is for VLSI designers and reliability engineers, particularly those who are working on the development of EOS/ESD analysis tools. CAD engineers working on development of circuit level and device level electrothermal simulators will also benefit from the material covered. This book will also be of interest to researchers and first and second year graduate students working in semiconductor devices and IC reliability fields.

Authors and Affiliations

  • Integrated Circuits Business Division, R&D Center, Hewlett-Packard Company, Palo Alto, USA

    Carlos H. Díaz

  • Coordinated Science Laboratory, University of Illinois, Urbana, USA

    Sung-Mo Kang

  • Semiconductor Process and Design Center, Texas Instruments Incorporated, Dallas, USA

    Charvaka Duvvury

Bibliographic Information

  • Book Title: Modeling of Electrical Overstress in Integrated Circuits

  • Authors: Carlos H. Díaz, Sung-Mo Kang, Charvaka Duvvury

  • Series Title: The Springer International Series in Engineering and Computer Science

  • DOI: https://doi.org/10.1007/978-1-4615-2788-6

  • Publisher: Springer New York, NY

  • eBook Packages: Springer Book Archive

  • Copyright Information: Kluwer Academic Publishers 1995

  • Hardcover ISBN: 978-0-7923-9505-8Published: 30 November 1994

  • Softcover ISBN: 978-1-4613-6205-0Published: 27 September 2012

  • eBook ISBN: 978-1-4615-2788-6Published: 06 December 2012

  • Series ISSN: 0893-3405

  • Edition Number: 1

  • Number of Pages: XXV, 148

  • Topics: Circuits and Systems, Electrical Engineering

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