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High-Level Power Analysis and Optimization

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  • © 1998

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Table of contents (6 chapters)

Keywords

About this book

High-Level Power Analysis and Optimization presents a comprehensive description of power analysis and optimization techniques at the higher (architecture and behavior) levels of the design hierarchy, which are often the levels that yield the most power savings. This book describes power estimation and optimization techniques for use during high-level (behavioral synthesis), as well as for designs expressed at the register-transfer or architecture level.
High-Level Power Analysis and Optimization surveys the state-of-the-art research on the following topics: power estimation/macromodeling techniques for architecture-level designs, high-level power management techniques, and high-level synthesis optimizations for low power.
High-Level Power Analysis and Optimization will be very useful reading for students, researchers, designers, design methodology developers, and EDA tool developers who are interested in low-power VLSI design or high-level design methodologies.

Authors and Affiliations

  • NEC, USA

    Anand Raghunathan, Sujit Dey

  • Princeton University, USA

    Niraj K. Jha

Bibliographic Information

  • Book Title: High-Level Power Analysis and Optimization

  • Authors: Anand Raghunathan, Niraj K. Jha, Sujit Dey

  • DOI: https://doi.org/10.1007/978-1-4615-5433-2

  • Publisher: Springer New York, NY

  • eBook Packages: Springer Book Archive

  • Copyright Information: Springer Science+Business Media New York 1998

  • Hardcover ISBN: 978-0-7923-8073-3Published: 30 November 1997

  • Softcover ISBN: 978-1-4613-7481-7Published: 21 November 2012

  • eBook ISBN: 978-1-4615-5433-2Published: 06 December 2012

  • Edition Number: 1

  • Number of Pages: XIX, 175

  • Topics: Circuits and Systems, Electrical Engineering, Computer-Aided Engineering (CAD, CAE) and Design

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