Access this chapter
Tax calculation will be finalised at checkout
Purchases are for personal use only
Preview
Unable to display preview. Download preview PDF.
References
Marques, A.M., V. Peluso, M.S.J. Steyaert, W. Sansen, “A 15-b Resolution 2-MHz Nyquist Rate ΣΔ ADC in a 1-µ m CMOS Technology,” IEEE J. Solid-State Circuits, Vol. 33, pp. 1065–1075, Jul. 1998.
Thanh, C.K., S.H. Lewis, P.J. Hurst, “A Second-Order Double-Sampled Delta-Sigma Modulator Using Individual-Level Averaging,” IEEE J. Solid-State Circuits, Vol. 32, pp. 1269–1273, Aug. 1997.
Chen, F. B.H. Leung, “A High Resolution Multibit Sigma-Delta Modulator with Individual Level Averaging,” IEEE J. Solid-State. Circuits, Vol. 30, pp. 453–460, Apr. 1995.
Burmas, T.V., K.C. Dyer, P.J. Hurst, S.H. Lewis, “A Second-Order Double-Sampled Delta-Sigma Modulator Using Additive-Error Switching,” IEEE J. Solid-State Circuits, Vol. 31, pp. 284–293, Mar. 1996.
Zwan, E.J. van der, E.C. Dijkmans, “A 0.2-mW CMOS ΣΔ Modulator for Speech Coding with 80 dB Dynamic Range,” IEEE J. Solid-State Circuits, Vol. 31, pp. 1873–1880, Dec. 1996.
Peluso, V., P. Vancorenland, A. Marques, M. Steyaert, W. Sansen, “A 900 mV 40µW Switched Opamp ΣΔ Modulator with 77 dB Dynamic Range,” ISSCC Dig. Tech. Papers, pp. 68–69, Feb. 1998.
Coban, A.L., P.E. Allen, “A 1.5V 1.0 mW Audio ΣΔ Modulator with 98 dB Dynamic Range” ISSCC Dig. Tech. Papers, pp. 50–51, Feb. 1999.
Geerts, Y., M. Steyaert, W. Sansen, “A 2.5 Msample/s Multi-bit ΣΔ CMOS ADC with 95 dB SNR,” ISSCC Dig. Tech. Papers, pp. 336–337, Feb. 2000.
Fujimori, I. L. Longo, A. Hairapetian, K. Seiyama, S. Kosic, J. Cao, S. Chan, “A 90 dB SNR, 2.5 MHz Output Rate ADC using cascaded Multibit ΣΔ Modulation at 8x Oversampling Ratio,” ISSCC Dig. Tech. Papers, pp. 338–339, Feb. 2000.
Geerts, Y., A. Marques, M. Steyaert, W. Sansen, “A 3.3 V 15-bit Delta-Sigma ADC with a Signal Bandwidth of 1.1 MHz for ADSL-Applications,” Proc. of ESSCIRC, pp. 168–171, Sep. 1998.
Rabii, S., B.A. Wooley, “A 1.8-V Digital-Audio Sigma-Delta Modulator in 0.8-µm CMOS,” IEEE J. Solid-State Circuits, Vol. 32, pp. 783–796, Jun. 1997.
Williams, L.A., B.A. Wooley, “A Third-Order Sigma-Delta Modulator with Extended Dynamic Range,” IEEE J. Solid-State. Circuits, Vol. 29, pp. 193–202, Mar. 1994.
Yin, G., F. Stubbe, W. Sansen, “A 16-b 320-kHz CMOS A/D Converter Using Two-Stage Third-Order ΣΔ Noise Shaping,” IEEE. J. Solid-State Circuits, Vol. 28, pp. 640–647, Jun. 1993.
Zwan, E.J. van der, “A 2.3 mW CMOS ΣΔ Modulator for Audio Applications,” ISSCC Dig. Tech. Papers, pp. 220–221, Feb. 1997.
Grilo, J., E. MacRobbie, R. Halim, G. Temes, “A 1.8V 94 dB Dynamic Range ΣΔ Modulator for Voice Applications,” ISSCC Dig. Tech. Papers, pp. 230–231, Feb. 1996.
Rabii, S., B.A. Wooley, “A 1.8V, 5.4 mW, Digital-Audio ΣΔ Modulator in 1.2µm CMOS,” ISSCC Dig. Tech. Papers, pp. 228–229, Feb. 1996.
CHen, F., and B. Leung, “A 0.25 mW Low-Pass Passive Sigma-Delta Modulator with Built-in Mixer for a 10-MHz IF Input,” IEEE. J. Solid-State Circuits, Vol. 32, pp. 774–782, Jun. 1997.
Jantzi, S.A., K.W. Martin, and A.S. Sedra, “Quadrature Bandpass ΣΔ Modulation for Digital Radio,” IEEE J. Solid-State Circuits, vol. 32, pp. 1935–1950, Dec. 1997.
Singor, F.W. and W.M. Snelgrove, “Switched-Capacitor Bandpass Delta-Sigma A/D Modulation at 10.7 MHz,” IEEE J. Solid-State. Circuits, Vol. 30, pp. 184–192, March 1995.
Song, B.S., “A Fourth-Order Bandpass Delta-Sigma Modulator with Reduced Number of Op Amps,” IEEE J. Solid-State Circuits, vol. 30, pp. 1309–1315, Dec. 1995.
Ong, A.K. and B.A. Wooley, “A Two-Path Bandpass ΣΔ Modulator for Digital IF Extraction at 20 MHz,” IEEE J. Solid-State Circuits, Vol. 32, pp. 1920–1934, Dec. 1997.
Hairapetian, A., “An 81 MHz IF Receiver in CMOS,” ISSCC Dig. Tech. Papers, pp. 56–57, Feb. 1996.
Engelen, J. van, R. van de Plassche, E. Stikvoort, A. Venes, “A 6th-Order Continuous-Time Bandpass ΣΔ Modulator for Digital Radio IF,” ISSCC Dig. Tech. Papers, pp. 56–57, Feb. 1999.
Tao, H., J.M. Khoury, “A 100 MHz IF, 400 M Sample/S CMOS Direct-Conversion Bandpass ΣΔ Modulator,” ISSCC Dig. Tech. Papers, pp. 60–61, Feb. 1999.
Namdar, A., B.H. Leung, “A 400 MHz 12 b 18 mW IF Digitizer with Mixer Inside a ΣΔ Modulator Loop,” ISSCC Dig. Tech. Papers, pp. 62–63, Feb. 1999.
Tabatabaei, A., K. Kaviani, B. Wooley, “A Two-Path Bandpass ΣΔ Modulator with Extended Noise Shaping,” ISSCC Dig. Tech. Papers, pp. 342–343, Feb. 2000.
Maurino, R., P. Mole, “A 200 MHz IF, 11 bit, 4th order Band-Pass ΣΔ ADC in SiGe,” Proc. of ESSCIRC, pp. 74–77, Sep. 1999.
Tonietto, D., P. Cusinato, F. Stefani, A. Baschirotto, “A 3.3V CMOS 10.7 MHz 6th-order bandpass ΣΔ modulator with 78 dB dynamic range,” Proc. of ESSCIRC, pp. 78–81, Sep. 1999.
Rights and permissions
Copyright information
© 2001 Kluwer Academic Publishers
About this chapter
Cite this chapter
(2001). Benchmark. In: Continuous-Time Sigma-Delta Modulation for A/D Conversion in Radio Receivers. The International Series in Engineering and Computer Science, vol 634. Springer, Boston, MA. https://doi.org/10.1007/0-306-48004-2_6
Download citation
DOI: https://doi.org/10.1007/0-306-48004-2_6
Publisher Name: Springer, Boston, MA
Print ISBN: 978-0-7923-7492-3
Online ISBN: 978-0-306-48004-1
eBook Packages: Springer Book Archive