Abstract
Very high-speed and low-area hardware architectures of the SHACAL-1 encryption algorithm are presented in this paper. The SHACAL algorithm was a submission to the New European Schemes for Signatures, Integrity and Encryption (NESSIE) project and it is based on the SHA-1 hash algorithm. Sub-pipelined SHACAL-1 encryption and decryption architectures are described and when implemented on Virtex-II XC2V4000FPGA devices, run at a throughput of 23 Gbps. In addition, fully pipelined and iterative architectures of the algorithm are presented. The SHACAL-1 decryption algorithm is derived and also presented in the paper, since it was not provided in the submission to NESSIE.
Access this chapter
Tax calculation will be finalised at checkout
Purchases are for personal use only
Preview
Unable to display preview. Download preview PDF.
References
US NIST Advanced Encryption Standard, (January, 2004) http://csrc.nist.gov/encryption/aes/
Z. Pan, S. Venkateswaran, S.T. Gurumani, and B.E. Wells, Exploiting Fine-Grain Parallelism present within the International Data Encryption Algorithm using a Xilinx FPGA, 16th International Conference on Parallel and Distributed Computing Systems (PDCS-2003), (Nevada, US, 2003).
G. Rouvroy, F.X. Standaert, J.J. Quisquater, J.D. Legat, Efficient FPGA Implementation of Block Cipher MISTY1, The Reconfigurable Architecture Workshop (RAW 2003), (Nice, France, 2003).
F.X. Standaert, G. Rouvroy, Efficient FPGA Implementation of Block Ciphers Khazad and MISTY1, 3rd NESSIE Workshop, http://www.di.ens.fr/wwwgrecc/NESSIE3/, (Germany, 2002).
T. Ichikawa, T. Sorimachi, T. Kasuya, M. Matsui, On the criteria of hardware evaluation of block ciphers(1), Technical report of IEICE, ISEC2001-53, (2001).
J.L. Beuchat, High Throughput Implementations of the RC6 Block Cipher Using Virtex-E and Virtex-II Devices, INRIA Research Report, http://perso.ens-lyon.fr/jean-luc.beuchat/publications.html, (July, 2002).
T. Ichikawa, T. Sorimachi, T. Kasuya, On Hardware Implementation of Block Ciphers Selected at the NESSIE Project Phase 1, 3rd NESSIE Workshop, http://www.di.ens.fr/wwwgrecc/NESSIE3/, (Germany, November 2002).
M. McLoone, J.V. McCanny, Very High Speed 17 Gbps SHACAL Encryption Architecture, 13th International Conference on Field Programmable Logic and Applications-FPL 2003, (Portugal, September 2003).
H. Handschuh, D. Naccache, SHACAL, 1st NESSIE Workshop, http://www.cosic.esat.kuleuven.ac.be/nessie/workshop/, (Belgium, November, 2000).
K.K. Ting, S.C.L. Yuen, K.H. Lee, P.H.W. Leong, An FPGA based SHA-256 Processor, 12th International Conference on Field Programmable Logic and Applications—FPL 2002, (France, September, 2002).
T. Grembowski, R. Lien, K. Gaj, N. Nguyen, P. Bellows, J. Flidr, T. Lehman, B. Schott, Comparative Analysis of the Hardware Implementations of Hash Functions SHA-1 and SHA-512, Information Security Conference”, (October, 2002).
M. McLoone, J.V. McCanny, Efficient Single-Chip Implementation of SHA-384 and SHA-512, IEEE International Conference on Field-Programmable Technology–FPT 2002), (Hong Kong, Dec 2002).
T. Kim, W. Jao, S. Tjiang, Circuit Optimization Using Carry-Save-Adder Cells, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 17, No. 10, (October, 1998).
G.P. Saggese, A. Mazzeo, N. Mazzocca, A.G.M. Strollo, An FPGA-Based Performance Analysis of the Unrolling, Tiling, and Pipelining of the AES Algorithm, 13th International Conference on Field Programmable Logic and Applications–FPL 2003, (Portugal, September, 2003).
M. McLoone, Hardware Performance Analysis of the SHACAL-2 Encryption Algorithm, submitted to IEE Proceedings-Circuits, Devices and Systems, (July, 2003).
NESSIE, Performance of Optimized Implementations of the NESSIE Primitives, http://www.cosic.esat.kuleuven.ac.be/nessie/deliverables/D21-v2.pdf, (February, 2003).
Author information
Authors and Affiliations
Editor information
Editors and Affiliations
Rights and permissions
Copyright information
© 2005 Springer
About this chapter
Cite this chapter
McLoone, M., McCanny, J. (2005). Performance Analysis of SHACAL-1 Encryption Hardware Architectures. In: Lysaght, P., Rosenstiel, W. (eds) New Algorithms, Architectures and Applications for Reconfigurable Computing. Springer, Boston, MA. https://doi.org/10.1007/1-4020-3128-9_20
Download citation
DOI: https://doi.org/10.1007/1-4020-3128-9_20
Publisher Name: Springer, Boston, MA
Print ISBN: 978-1-4020-3127-4
Online ISBN: 978-1-4020-3128-1
eBook Packages: EngineeringEngineering (R0)