Abstract
This paper describes the implementation of a second generation Bluetooth single chip in 0.13um technology. The considerations in the concept phase on technology and topology level are highlighted. The main targeted market segment is the cellular applications, urging for very low power consumption in all operation modes. The presented chip presents a very competitive consumption in active operation and also an excellent powerdown current consumption. The physical layer implementation of the transmitter part of the chip is presented as a case study of the active power reduction.
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References
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Borremans, M., Goetschalckx, P. (2006). Low Power Bluetooth Single-Chip Design. In: Steyaert, M., Huijsing, J., van Roermund, A. (eds) Analog Circuit Design. Springer, Dordrecht. https://doi.org/10.1007/1-4020-3885-2_3
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DOI: https://doi.org/10.1007/1-4020-3885-2_3
Publisher Name: Springer, Dordrecht
Print ISBN: 978-1-4020-3884-6
Online ISBN: 978-1-4020-3885-3
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