Abstract
A bandpass ADC digitizes a bandpass signal directly, without prior conversion to baseband. Bandpass ADCs are well-suited to wired and wireless receivers, and can reduce system complexity, increase integration and improve performance. This paper describes architectures for bandpass and quadrature bandpass ADCs and examines several circuit considerations associated with operation at sampling rates in the 100-MHz range.
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References
T. H. Pearce and A. C. Baker, “Analogue to digital conversion requirements for HF radio receivers,” Proceedings of the IEE Colloquium on system aspects and applications of ADCs for radar, sonar and communications, London, Nov. 1987, Digest No. 1987/92.
S. A. Jantzi, K. W. Martin and A. S. Sedra, “Quadrature bandpass Δ∑ modulation for digital radio,” IEEE Journal of Solid-State Circuits, vol. 32, no. 12, pp. 1935–1950, Dec. 1997.
G. Raghavan, J. F. Jensen, J. Laskowski, M. Kardos, M. G. Case, M. Sokolich and S. Thomas III, “Architecture, design, and test of continuous-time tunable intermediate-frequency bandpass delta-sigma modulators,” IEEE Journal of Solid-State Circuits, vol. 36, no. 1, pp. 5–13, Jan. 2001.
J. Van Engelen and R. Van De Plassche, Bandpass sigma delta modulators— stability analysis, performance and design aspects, Norwell, MA: Kluwer Academic Publishers 1999.
R. Schreier and G. C. Temes, Understanding Delta-Sigma Data Converters, John Wiley & Sons Inc., Hoboken, New Jersey, 2005.
L. J. Breems et al., “A cascaded continuous-time Δ∑modulator with 67 dB dynamic range in 10 MHz bandwidth,” IEEE International Solid-State Circuits Conference Digest of Technical Papers, pp. 72–73, Feb. 2004.
J. A. E. P. Van Engelen, R.J. Van De Plassche, E. Stikvoort and A. G. Venes, “A sixth-order continuous-time bandpass sigma-delta modulator for digital radio IF,” IEEE Journal of Solid-State Circuits, vol. 34, no. 12, pp. 1753–1764, Dec. 1999.
R. Schreier, J. Lloyd, L. Singer, D. Paterson, M. Timko, M. Hensley, G. Patterson, K. Behel, J. Zhou and W. J, Martin, “A 10-300 MHz IF-digitizing IC with 90-105 dB dynamic range and 15-333 kHz bandwidth,” IEEE Journal of Solid-State Circuits, vol. 37, no. 12, pp. 1636–1644, December 2002.
W. Schofield, D. Mercer, and L.S. Onge, “A 16b 400MS/s DAC with <–80 dBc IMD to 300 MHz and <–160 dBm/Hz noise power spectral density, IEEE International Solid-State Circuits Conference Digest of Technical Papers, pp. 126–127, Feb. 2003.
T. Shui and R. Schreier, “Mismatch shaping for a current-mode multibit delta-sigma DAC,” IEEE Journal of Solid-State Circuits, vol. 34, pp. 331–338, March 1999.
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© 2006 Springer
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Schreier, R. (2006). HIGH-SPEED BANDPASS ADCs. In: Steyaert, M., Huijsing, J., **, M. (eds) Analog Circuit Design. Springer, Dordrecht. https://doi.org/10.1007/1-4020-3885-2_5
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DOI: https://doi.org/10.1007/1-4020-3885-2_5
Publisher Name: Springer, Dordrecht
Print ISBN: 978-1-4020-3884-6
Online ISBN: 978-1-4020-3885-3
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