Transistor-Level Combinational Timing Optimization

Summary

This chapter has overviewed several methods that can be used for transistor-level timing optimization of digital circuits. The specific methods overviewed include transistor sizing, dual V _t optimization, and padding for short paths. These are intended to provide a flavor for timing optimization and should not be construed as a complete review of such methods. In addition to these, numerous methods for interconnect optimization using buffer insertion and wire sizing have been proposed in the literature. Even more such techniques are on the way: for instance, recent technologies have seen large increases in the gate leakage (as opposed to the subthreshold leakage, addressed in Section 8.8), which can be translated into a leakage/delay tradeoff problem by using dual oxide thickness (T _ox ) values.