Abstract
Over the last few years, there has been increasing emphasis on integrating ready-made components (IP, cores) into complex System on a Chip (SoC) designs. The verification of such designs poses new challenges. At the heart of these challenges lies the requirement to verify the integration of several previously designed components in a relatively short time. Simulation-based methods are the main verification vehicle used for system-level functional verification of SoC designs; therefore, stimuli generation plays an important role in this field.
Our work offers a solution for efficiently dealing with the verification of systems with multiple configurations and derivative systems, a common challenge in the context of system verification. We present a generation scheme in which the system behavior is defined using a combination of transaction-based modeling, local component behavior, and the topology of the system. We show how this approach allows the implementation of the verification plan using high level constructs and promotes the reuse of verification IP between systems.
The ideas described below were implemented as part of X-Gen, a system-level test-case generator developed and used in IBM.
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Copty, S., Jaeger, I., Katz, Y. (2006). Path-Based System Level Stimuli Generation. In: Ur, S., Bin, E., Wolfsthal, Y. (eds) Hardware and Software, Verification and Testing. HVC 2005. Lecture Notes in Computer Science, vol 3875. Springer, Berlin, Heidelberg. https://doi.org/10.1007/11678779_1
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DOI: https://doi.org/10.1007/11678779_1
Publisher Name: Springer, Berlin, Heidelberg
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