Abstract
We have presented our stepwise approach to the design of an architecture for a multiprocessor reduction machine, starting from requirements induced by the language and by architectural considerations.
Perhaps the most important feature of the machine is the load balancing mechanism, that includes the decentralized computation and distribution of an instantaneous load information, allowing tasks to be equally distributed among processors. Furthermore, this load information allows each reduction processor to dynamically change its execution model, thus contributing to the regulation of the instantaneous parallelism in the machine. We also saw how information concerning management of potential parallelism can be conveyed by combinators themselves.
More details of this architecture, such as the network organization, garbage collector, etc., and details concerning compilation, can be found in [Castan85, Castan86a, Castan86b, Lemaître86].
This research is supported by the DGA/STPA under contract STPA no 8595004.07
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Castan, M. et al. (1987). Toward the design of a parallel graph reduction machine the MaRS project. In: Fasel, J.H., Keller, R.M. (eds) Graph Reduction. GR 1986. Lecture Notes in Computer Science, vol 279. Springer, Berlin, Heidelberg. https://doi.org/10.1007/3-540-18420-1_54
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DOI: https://doi.org/10.1007/3-540-18420-1_54
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