CMOL: Devices, Circuits, and Architectures

Abstract

This chapter is a brief review of the recent work on various aspects of the prospective hybrid semiconductor/nanowire/molecular (“CMOL”) integrated circuits. The basic idea of such circuits is to combine the advantages of the currently dominating CMOS technology (including its flexibility and high fabrication yield) with those of molecular devices with nanometer-scale footprint. Two-terminal molecular devices would be self-assembled on a pre-fabricated nanowire crossbar fabric, enabling very high function density at acceptable fabrication costs. Preliminary estimates show that the density of active devices in CMOL circuits may be as high as 10¹² cm^-2 and that they may provide an unparalleled information processing performance, up to 10²⁰ operations per cm² per second, at manageable power consumption. However, CMOL technology imposes substantial requirements (most importantly, that of high defect tolerance) on circuit architectures. In the view of these restrictions, the most straightforward application of CMOL circuits is terabitscale memories, in which powerful bad-bit-exclusion and error-correction techniques may be used to boost the defect tolerance. The implementation of Boolean logic circuits is more problematic, though our preliminary results for reconfigurable, uniform FPGA-like CMOL circuits look very encouraging. Finally, CMOL technology seems to be uniquely suitable for the implementation of the “CrossNet” family of neuromorphic networks for advanced information processing including, at least, pattern recognition and classification, and quite possibly much more intelligent tasks. We believe that these application prospects justify a large-scale research and development effort focused on the main challenge of the field, the high-yield self-assembly of molecular devices.