Abstract
We propose in this paper a processor architecture that supports multi instructions set through run time functional assignment algorithm (RUNFA). The above processor, which is named Functional Assignment Register Microprocessor (FaRM-rq) supports queue and register based instruction set architecture and functions into different modes: (1) R-mode (FRM) - when switched for register based instructions support, and (2) Q-mode (FQM) - when switched for Queue based instructions support. The entities share a common data path and may operate independently though not in parallel.
In FRM mode, the machine’s shared storage unit (SSU) behaves as a conventional register file. However, in FQM mode, the system organizes the SSU access as a first-in-first-out latches, thus accesses concentrate around a small window and the addressing of registers is implicit trough the Queue head and tail pointers.
First, we present the novel aspects of the FaRM-rq1 architecture. Then, we give the novel FQM fundamentals and the principles underlying the architecture.
The above architecture embraces multiprogramming languages and will combine the best features of Queue, Register and Stack models of computing.
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Abderazek, B.A., Shigeta, S., Yoshinaga, T., Sowa, M. (2003). On the Design of a Register Queue Based Processor Architecture (FaRM-rq). In: Guo, M., Yang, L.T. (eds) Parallel and Distributed Processing and Applications. ISPA 2003. Lecture Notes in Computer Science, vol 2745. Springer, Berlin, Heidelberg. https://doi.org/10.1007/3-540-37619-4_26
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DOI: https://doi.org/10.1007/3-540-37619-4_26
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