Abstract
This paper focuses on the implementation over FPL devices of high throughput DSP applications taking advantage of RNS arithmetic. The synergy between the RNS and modern FPGA device families, providing built-in tables and fast carry and cascade chains, makes it possible to accelerate MAC intensive real-time and DSP systems. In this way, a slow high dynamic range binary 2’s complement system can be partitioned into various parallel and high throughput small word-length RNS channels without inter-channel carry dependencies. To illustrate the design methodology, novel RNS-based architectures for multi-octave orthogonal DWT and its inverse are implemented using structural level VHDL synthesis. Area analysis and performance simulation are conducted. A relevant throughput improvement for the proposed RNS-based solution is obtained, compared to the equivalent 2’s complement implementation.
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References
M. Soderstrand, W. Jenkins, G. A. Jullien, and F. J. Taylor, Residue Number System Arithmetic: Modern Applications in Digital Signal Processing. IEEE Press Reprint Series. IEEE Press, 1986.
N. Szabo and R. Tanaka, Residue Arithmetic and its Applications to Computer Technology. McGraw-Hill, 1967.
A. García, U. Meyer-Bäse, A. Lloris and F. J. Taylor, “RNS Implementation of FIR Filters Based on Distributed Arithmetic using Field-Programmable Logic”, Proc. IEEE Int. Symp. on Circuits and Systems, Orlando, FL, vol. 1, pp. 486–489, Jun. 1999.
J. Ramírez, A. García, P. G. Fernández, L. Parrilla and A. Lloris, “A New Architecture to Compute the Discrete Cosine Transform Using the Quadratic Residue Number System,” Proc. of 2000 IEEE Int. Symp. on Circuits and Systems, Geneva, 2000, vol. 5, pp. 321–324.
Altera Corporation, 1998 Data Book, Jan. 1998.
Xilinx Inc., The Programmable Logic Data Book, 1999.
Actel Corporation, ProASIC 500K Family Data Sheet, 2000.
M. A. Bayoumi, G. A. Jullien and W. C. Miller, “A VLSI Implementation of Residue Adders.” IEEE Trans. on Circuits and systems, vol. 34, no. 3, pp. 284–288, Mar. 87.
G. Strang, T. Nguyen, Wavelets and Filter Banks, Wellesly-Cambridge Press, 1997.
M. Vetterli, J. Kovacevik, Wavelets and Subband Coding, Prentice Hall, 1995
C. Chakrabarti, C. Mumford, “Efficient Realizations of Encoders and Decoders Based on the 2-D Discrete Wavelet Transform,” IEEE Trans. VLSI Syst., vol. 2, no. 3, Sep. 1999.
M. Vishwanath, M. Owens, M. J. Irwin, “VLSI Architectures for the Discrete Wavelet Transform,” IEEE Trans. Circuits Syst. II, vol. 42, no. 5, May 1995.
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Ramírez, J., García, A., Fernández, P.G., Parrilla, L., Lloris, A. (2000). Analysis of RNS-FPL Synergy for High Throughput DSP Applications: Discrete Wavelet Transform. In: Hartenstein, R.W., Grünbacher, H. (eds) Field-Programmable Logic and Applications: The Roadmap to Reconfigurable Computing. FPL 2000. Lecture Notes in Computer Science, vol 1896. Springer, Berlin, Heidelberg. https://doi.org/10.1007/3-540-44614-1_37
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DOI: https://doi.org/10.1007/3-540-44614-1_37
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