Abstract
In this paper, we present an incremental clustering technique for LUT-based sequential circuits targetting a delay-optimized partitioning of the LUT and latch blocks for FPGA placement. Our cost function considers a slack-based relative delay criticality of circuit nets. As partitions are being constructed simultaneously, the method is open also for further evaluation criteria, e.g. in respect of placeability or routability.
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Wolz, F., Kolla, R. (2001). Bubble Partitioning for LUT-Based Sequential Circuits. In: Brebner, G., Woods, R. (eds) Field-Programmable Logic and Applications. FPL 2001. Lecture Notes in Computer Science, vol 2147. Springer, Berlin, Heidelberg. https://doi.org/10.1007/3-540-44687-7_35
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DOI: https://doi.org/10.1007/3-540-44687-7_35
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