Abstract
Interconnection planning is becoming an important design issue for large FPGA based designs and ASICs. One of the most important issues for planning interconnection is the ability to predict the routability of a given design. In this paper, we introduce a new methodology, fGREP, for ultra-fast estimation of routing demands for placed circuits on FPGAs. Our method uses logic block fanout as a measure of available routing alternatives for routing a net. Experimental results on a large set of benchmark examples show that our predictions closely match with the detailed routing results of a well known router, namely VPR[1]. fGREP is simultaneously able to predict the peak routing demand (channel width) and the routing demands for every routing channel. It is currently used for postplacement estimation of routing demands, but can be used during the placement process also. fGREP can be used with any standard FPGA place and route flow.
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Kannan, P., Balachandran, S., Bhatia, D. (2001). fGREP - Fast Generic Routing Demand Estimation for Placed FPGA Circuits. In: Brebner, G., Woods, R. (eds) Field-Programmable Logic and Applications. FPL 2001. Lecture Notes in Computer Science, vol 2147. Springer, Berlin, Heidelberg. https://doi.org/10.1007/3-540-44687-7_5
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DOI: https://doi.org/10.1007/3-540-44687-7_5
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