Abstract
We demonstrate the importance of reducing misses in the translation-lookaside buffer (TLB) for obtaining good performance on modern computer architectures. We focus on data structures for the dynamic predecessor problem: to maintain a set S of keys from a totally ordered universe under insertions, deletions and predecessor queries. We give two general techniques for simultaneously reducing cache and TLB misses: simulating 3-level hierarchical memory algorithms and cache-oblivious algorithms. We give preliminary experimental results which demonstrate that data structures based on these ideas outperform data structures which are based on minimising cache misses alone, namely B-tree variants.
Research supported in part by EPSRC grant GR/L92150 (Rahman, Raman), NSF grant CCR-98-00085 (Cole) and UISTRF project 2001.04/IT (Raman).
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Rahman, N., Cole, R., Raman, R. (2001). Optimised Predecessor Data Structures for Internal Memory. In: Brodal, G.S., Frigioni, D., Marchetti-Spaccamela, A. (eds) Algorithm Engineering. WAE 2001. Lecture Notes in Computer Science, vol 2141. Springer, Berlin, Heidelberg. https://doi.org/10.1007/3-540-44688-5_6
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DOI: https://doi.org/10.1007/3-540-44688-5_6
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