Abstract
Power dissipation due to the steering logic, that is, the multiplexer network and the interconnect, can usually account for a significant fraction of the total power budget. In this work, we present RTL power models for these two types of architectural elements. The multiplexer model leverages existing scalable models, and can be used for special complex types with re-configurable numbers of data bits and ways. The interconnect model is obtained by empirically relating capacitance to circuit area, that is either estimated by means of statistical models or extracted from back-annotation information available at the gate level.
This work was supported, in part, by the EC under grant n. 27696 “PEOPLE”.
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Anton, C., Bogliolo, A., Civera, P., Colonescu, I., Macii, E., Poncino, M. (2000). RTL Estimation of Steering Logic Power. In: Soudris, D., Pirsch, P., Barke, E. (eds) Integrated Circuit Design. PATMOS 2000. Lecture Notes in Computer Science, vol 1918. Springer, Berlin, Heidelberg. https://doi.org/10.1007/3-540-45373-3_5
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DOI: https://doi.org/10.1007/3-540-45373-3_5
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