Abstract
Standard cell libraries have been successfully used for years, however with the emergence of new technologies and the increasing complexity of designs, this concept becomes less and less attractive. Most of the time, cells are too generic and not well suited to the block being created. As a result the final design is not well optimized in terms of timing, power and area.
This paper describes a new approach based on transistor level layout synthesis for CMOS IP cores rapid prototyping (~100k transistors).
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Landrault, A., Pellier, L., Richard, A., Jay, C., Robert, M., Auvergne, D. (2002). Transistor Level Synthesis Dedicated to Fast I.P. Prototyping. In: Hochet, B., Acosta, A.J., Bellido, M.J. (eds) Integrated Circuit Design. Power and Timing Modeling, Optimization and Simulation. PATMOS 2002. Lecture Notes in Computer Science, vol 2451. Springer, Berlin, Heidelberg. https://doi.org/10.1007/3-540-45716-X_16
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DOI: https://doi.org/10.1007/3-540-45716-X_16
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